From d198238c7fa77e64eb51d82e73040d67206a7b00 Mon Sep 17 00:00:00 2001 From: Code4me2 Date: Sun, 16 Aug 2026 11:54:48 -0700 Subject: [PATCH] nvidia: don't report fake PCIe link on unified-memory SoC GPUs On unified-memory SoC platforms such as the DGX Spark (GB10), the GPU is attached via an on-die interconnect (NVLink-C2C) rather than a PCIe link. NVML nevertheless returns NVML_SUCCESS for the current PCIe link generation/width, but with placeholder values (GEN 1 @ 1x), which nvtop surfaces as if they were real. Since unified-memory devices have no PCIe framebuffer link, only report PCIe link generation/width on discrete (non-unified) GPUs so the header falls back to N/A instead of showing a misleading link. Pcie RX/TX throughput already shows N/A on these devices because NVML returns NVML_ERROR_NOT_SUPPORTED there. Closes the PCIe misreporting part of #426. --- src/extract_gpuinfo_nvidia.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/src/extract_gpuinfo_nvidia.c b/src/extract_gpuinfo_nvidia.c index 33670a60..b5e470cb 100644 --- a/src/extract_gpuinfo_nvidia.c +++ b/src/extract_gpuinfo_nvidia.c @@ -702,14 +702,20 @@ static void gpuinfo_nvidia_refresh_dynamic_info(struct gpu_info *_gpu_info) { } // Pcie generation used by the device - last_nvml_return_status = nvmlDeviceGetCurrPcieLinkGeneration(device, &dynamic_info->pcie_link_gen); - if (last_nvml_return_status == NVML_SUCCESS) - SET_VALID(gpuinfo_pcie_link_gen_valid, dynamic_info->valid); - - // Pcie width used by the device - last_nvml_return_status = nvmlDeviceGetCurrPcieLinkWidth(device, &dynamic_info->pcie_link_width); - if (last_nvml_return_status == NVML_SUCCESS) - SET_VALID(gpuinfo_pcie_link_width_valid, dynamic_info->valid); + // On unified-memory SoC platforms (e.g. DGX Spark / GB10) the device is not + // attached through a PCIe link but via its own on-die interconnect + // (NVLink-C2C). NVML still reports placeholder values here (GEN 1 @ 1x) that + // would be misleading, so only report them on discrete GPUs. + if (!has_unified_memory) { + last_nvml_return_status = nvmlDeviceGetCurrPcieLinkGeneration(device, &dynamic_info->pcie_link_gen); + if (last_nvml_return_status == NVML_SUCCESS) + SET_VALID(gpuinfo_pcie_link_gen_valid, dynamic_info->valid); + + // Pcie width used by the device + last_nvml_return_status = nvmlDeviceGetCurrPcieLinkWidth(device, &dynamic_info->pcie_link_width); + if (last_nvml_return_status == NVML_SUCCESS) + SET_VALID(gpuinfo_pcie_link_width_valid, dynamic_info->valid); + } // Pcie reception throughput last_nvml_return_status = nvmlDeviceGetPcieThroughput(device, NVML_PCIE_UTIL_RX_BYTES, &dynamic_info->pcie_rx);