From 2ff2118ab4b3efe600a2cd8acbc1e1f032fcbc05 Mon Sep 17 00:00:00 2001
From: Aamir Abdul Azeez <165933255+aamir-azeez@users.noreply.github.com>
Date: Sat, 26 Sep 2026 22:43:33 -0400
Subject: [PATCH] Save casez statements in generated Verilog

---
 pyverilog/ast_code_generator/codegen.py       |  3 ++
 .../template/casezstatement.txt               |  5 +++
 .../ast_code_generator_test/test_ast_casez.py | 32 +++++++++++++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 pyverilog/ast_code_generator/template/casezstatement.txt
 create mode 100644 tests/ast_code_generator_test/test_ast_casez.py

diff --git a/pyverilog/ast_code_generator/codegen.py b/pyverilog/ast_code_generator/codegen.py
index 9b87569..b50425d 100644
--- a/pyverilog/ast_code_generator/codegen.py
+++ b/pyverilog/ast_code_generator/codegen.py
@@ -770,6 +770,9 @@ def visit_CasexStatement(self, node):
         rslt = template.render(template_dict)
         return rslt
 
+    def visit_CasezStatement(self, node):
+        return self.visit_CaseStatement(node)
+
     def visit_Case(self, node):
         filename = getfilename(node)
         template = self.get_template(filename)
diff --git a/pyverilog/ast_code_generator/template/casezstatement.txt b/pyverilog/ast_code_generator/template/casezstatement.txt
new file mode 100644
index 0000000..4a897b1
--- /dev/null
+++ b/pyverilog/ast_code_generator/template/casezstatement.txt
@@ -0,0 +1,5 @@
+casez({{ comp }})
+{%- for case in caselist %}
+{{ case }}
+{%- endfor %}
+endcase
diff --git a/tests/ast_code_generator_test/test_ast_casez.py b/tests/ast_code_generator_test/test_ast_casez.py
new file mode 100644
index 0000000..8e481cb
--- /dev/null
+++ b/tests/ast_code_generator_test/test_ast_casez.py
@@ -0,0 +1,32 @@
+from io import StringIO
+
+import pytest
+
+from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+from pyverilog.vparser.parser import VerilogParser
+
+
+@pytest.mark.parametrize("keyword", ["case", "casex", "casez"])
+def test_case_statement_roundtrip(tmp_path, keyword):
+    source = """
+module top(input [3:0] selector, output reg [3:0] result);
+  always @* begin
+    %s(selector)
+      4'b1???, 4'b0zzz: result = selector;
+      default: begin
+        result = 4'bxxxx;
+      end
+    endcase
+  end
+endmodule
+""" % keyword
+    parser = VerilogParser(outputdir=str(tmp_path), debug=False)
+    original = parser.parse(source)
+    generated = ASTCodeGenerator().visit(original)
+
+    reparsed = parser.parse(generated)
+    original_tree = StringIO()
+    reparsed_tree = StringIO()
+    original.show(original_tree, showlineno=False)
+    reparsed.show(reparsed_tree, showlineno=False)
+    assert original_tree.getvalue() == reparsed_tree.getvalue()