From 069c0bc4703d0ab3f6344a380dfda165650b926b Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Thu, 18 Jun 2026 17:35:05 +0200 Subject: [PATCH 01/18] write local configuration automatically on initial regression run (cherry picked from commit 488c68cd4fae4003498038335054b19a58a1ef2b) --- regression.tcl | 6 +++++- tools/poc.tcl | 11 +++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/regression.tcl b/regression.tcl index c2239fb82..69d6debd6 100644 --- a/regression.tcl +++ b/regression.tcl @@ -63,7 +63,7 @@ namespace import ::regression::* # Configuration space # #---------------------# set defaultStep "all" -set regressionLevels [createRegressionLevels osvvm poc test] ; # all +set regressionLevels [createRegressionLevels osvvm poc test] ; # clean, all # -P -projectRoot set project folder root for poc scripting # -g -gui disables system exit (i.e. on errors) @@ -82,6 +82,10 @@ configureOSVVM -stop 1 ; evaluateRegressionLevel $defaultStep $regressionLevels +if {![file exists $::poc::localConfigurationPath] || $::regression::level == -1} { + ::poc::WriteLocalConfiguration +} + if {$::regression::level <= 0} { build ${root}/lib/OsvvmLibraries.pro [BuildName "${::poc::buildNamePrefix}OsvvmLibraries"] if {[checkForBuildErrors] || $::regression::executeSingleStep} { diff --git a/tools/poc.tcl b/tools/poc.tcl index dea0fca90..4e443b5ef 100644 --- a/tools/poc.tcl +++ b/tools/poc.tcl @@ -181,6 +181,16 @@ Other tools: set ::poc::localConfigurationPath [file join ${::poc::localConfigurationFolder} ${::poc::localConfigurationFile}] } + proc WriteLocalConfiguration {} { + set content "package local_configuration is\n" + append content "\tconstant LOCAL_PROJECT_DIR : string := \"$::poc::projectRoot\";\n" + append content "end package;\n" + + set fileHandle [open $::poc::localConfigurationPath "w"] + puts -nonewline $fileHandle $content + close $fileHandle + } + proc checkForBuildErrors {} { if {$::osvvm::AnalyzeErrorCount > 0} { puts "ERROR: While building $::osvvm::LastBuildName" @@ -235,6 +245,7 @@ puts "Loaded PoC extensions for OSVVM." namespace eval ::regression { proc createRegressionLevels {args} { + set map(clean) -1 set map(all) 0 set i 0 From 2fb82ec4a3e09f67cd6654764ca6c58ebfb8a3ef Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Thu, 18 Jun 2026 23:28:40 +0200 Subject: [PATCH 02/18] remove inner generate label --- src/mem/ocram/ocram_EnhancedSimpleDualPort.vhdl | 6 +++--- src/mem/ocram/ocram_SimpleDualPort.vhdl | 4 ++-- src/mem/ocram/ocram_SinglePort.vhdl | 4 ++-- src/mem/ocram/ocram_TrueDualPort.vhdl | 6 +++--- tb/bus/axi4lite/OCRAM_Adapter/TC_InitMemory.vhdl | 6 +++--- .../axi4lite_OCRAM_Adapter_TestController.vhdl | 2 +- 6 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mem/ocram/ocram_EnhancedSimpleDualPort.vhdl b/src/mem/ocram/ocram_EnhancedSimpleDualPort.vhdl index 3a174f2cb..fbbfe3f3f 100644 --- a/src/mem/ocram/ocram_EnhancedSimpleDualPort.vhdl +++ b/src/mem/ocram/ocram_EnhancedSimpleDualPort.vhdl @@ -116,7 +116,7 @@ architecture rtl of ocram_EnhancedSimpleDualPort is constant DEPTH : positive := 2**ADDRESS_BITS; begin - gen: if gInfer: not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate + gen: if not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate -- For Xilinx ISE, Xilinx Vivado and Lattice LSE we can reuse the ocram_TrueDualPort. -- -- **Attention**: This encapsulation is mandatory for Xilinx Vivado, @@ -142,7 +142,7 @@ begin PortB_DataIn => (others => '0'), PortB_DataOut => PortB_DataOut ); - elsif gAltera: not SIMULATION and (VENDOR = VENDOR_ALTERA) generate + elsif not SIMULATION and (VENDOR = VENDOR_ALTERA) generate -- Direct instantiation of altsyncram (including component -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. @@ -167,7 +167,7 @@ begin PortB_DataIn => (others => '0'), PortB_DataOut => PortB_DataOut ); - elsif gSim: SIMULATION generate + elsif SIMULATION generate tdp: component ocram_TrueDualPort_Simulation -- XXX: why is this not a second architecture? generic map ( ADDRESS_BITS => ADDRESS_BITS, diff --git a/src/mem/ocram/ocram_SimpleDualPort.vhdl b/src/mem/ocram/ocram_SimpleDualPort.vhdl index fc8c33ae4..6bec0bd4c 100644 --- a/src/mem/ocram/ocram_SimpleDualPort.vhdl +++ b/src/mem/ocram/ocram_SimpleDualPort.vhdl @@ -87,7 +87,7 @@ architecture rtl of ocram_SimpleDualPort is constant DEPTH : positive := 2**ADDRESS_BITS; begin - gen: if gInfer: not SIMULATION and ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate + gen: if not SIMULATION and ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate -- RAM can be inferred correctly -- Xilinx notes: -- WRITE_MODE is set to WRITE_FIRST, but this also means that read data @@ -121,7 +121,7 @@ begin end if; end if; end process; - elsif gSim: SIMULATION generate + elsif SIMULATION generate begin sim_tdp: ocram_TrueDualPort_Simulation generic map ( diff --git a/src/mem/ocram/ocram_SinglePort.vhdl b/src/mem/ocram/ocram_SinglePort.vhdl index 2754d8766..ab15f4da1 100644 --- a/src/mem/ocram/ocram_SinglePort.vhdl +++ b/src/mem/ocram/ocram_SinglePort.vhdl @@ -83,7 +83,7 @@ architecture rtl of ocram_SinglePort is constant DEPTH : positive := 2**ADDRESS_BITS; begin - gen: if gInfer: (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate + gen: if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate signal ram : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); signal a_reg : unsigned(ADDRESS_BITS-1 downto 0); @@ -102,7 +102,7 @@ begin end process; DataOut <= (others => 'X') when SIMULATION and is_x(std_logic_vector(a_reg)) else ram(to_integer(a_reg)); -- gets new data - elsif gAltera: VENDOR = VENDOR_ALTERA generate + elsif VENDOR = VENDOR_ALTERA generate component ocram_SimplePort_Altera generic ( ADDRESS_BITS : positive; diff --git a/src/mem/ocram/ocram_TrueDualPort.vhdl b/src/mem/ocram/ocram_TrueDualPort.vhdl index e8444509d..fdf6dcfc1 100644 --- a/src/mem/ocram/ocram_TrueDualPort.vhdl +++ b/src/mem/ocram/ocram_TrueDualPort.vhdl @@ -105,7 +105,7 @@ architecture rtl of ocram_TrueDualPort is constant DEPTH : positive := 2**ADDRESS_BITS; begin - gen: if gInfer: not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate + gen: if not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate signal ram : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); signal a1_reg : unsigned(ADDRESS_BITS-1 downto 0) := (others => 'U'); signal a2_reg : unsigned(ADDRESS_BITS-1 downto 0) := (others => 'U'); @@ -136,7 +136,7 @@ begin PortA_DataOut <= (others => 'X') when SIMULATION and is_x(std_logic_vector(a1_reg)) else ram(to_integer(a1_reg)); -- returns new data PortB_DataOut <= (others => 'X') when SIMULATION and is_x(std_logic_vector(a2_reg)) else ram(to_integer(a2_reg)); -- returns new data - elsif gAltera: not SIMULATION and (VENDOR = VENDOR_ALTERA) generate + elsif not SIMULATION and (VENDOR = VENDOR_ALTERA) generate -- Direct instantiation of altsyncram (including component -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. @@ -162,7 +162,7 @@ begin PortB_DataIn => PortB_DataIn, PortB_DataOut => PortB_DataOut ); - elsif gSim: SIMULATION generate + elsif SIMULATION generate sim_tdp: ocram_TrueDualPort_Simulation generic map ( ADDRESS_BITS => ADDRESS_BITS, diff --git a/tb/bus/axi4lite/OCRAM_Adapter/TC_InitMemory.vhdl b/tb/bus/axi4lite/OCRAM_Adapter/TC_InitMemory.vhdl index 1322a76cb..590582117 100644 --- a/tb/bus/axi4lite/OCRAM_Adapter/TC_InitMemory.vhdl +++ b/tb/bus/axi4lite/OCRAM_Adapter/TC_InitMemory.vhdl @@ -26,9 +26,9 @@ begin begin -- Initialization of test SetAlertLogName("TC_InitMemory") ; - SetLogEnable(PASSED, TRUE); - SetLogEnable(INFO, TRUE); - SetLogEnable(DEBUG, TRUE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, FALSE); + SetLogEnable(DEBUG, FALSE); -- Wait for testbench initialization wait for 0 ns ; diff --git a/tb/bus/axi4lite/OCRAM_Adapter/axi4lite_OCRAM_Adapter_TestController.vhdl b/tb/bus/axi4lite/OCRAM_Adapter/axi4lite_OCRAM_Adapter_TestController.vhdl index 219341120..2f1e26040 100644 --- a/tb/bus/axi4lite/OCRAM_Adapter/axi4lite_OCRAM_Adapter_TestController.vhdl +++ b/tb/bus/axi4lite/OCRAM_Adapter/axi4lite_OCRAM_Adapter_TestController.vhdl @@ -61,7 +61,7 @@ entity axi4lite_OCRAM_Adapter_TestController is -- access RAM through external name --alias DATA_BITS is <>; -- WORKAROUND: NVC 1.20.1 - Size of unconstrained datatype not propagated through ext. name --alias DEPTH is <>; -- WORKAROUND: NVC 1.20.1 - Size of unconstrained datatype not propagated through ext. name - alias ram is <>; --(0 to DEPTH - 1)(DATA_BITS - 1 downto 0)>>; + alias ram is <>; --(0 to DEPTH - 1)(DATA_BITS - 1 downto 0)>>; -- Not currently used in the Axi4Lite model - future use for Axi4Lite Burst Emulation modes -- alias WriteBurstFifo is <> ; From 56766f802c9f1e96817a60b920b5dc2d6851bde3 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Thu, 18 Jun 2026 23:29:11 +0200 Subject: [PATCH 03/18] update fifo-ic-git constraint to new generates --- ucf/fifo/fifo_ic_got.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ucf/fifo/fifo_ic_got.xdc b/ucf/fifo/fifo_ic_got.xdc index 395ff7769..667c06f03 100644 --- a/ucf/fifo/fifo_ic_got.xdc +++ b/ucf/fifo/fifo_ic_got.xdc @@ -3,6 +3,6 @@ # Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. # set max delay between regfile write and read side lower clock period -set_max_delay -from [get_cells -regexp {gSmall\.regfile.*/.*|gLarge\.ram/gInfer.ram_reg.*/.*}] \ - -to [get_cells -regexp {gSmall\.do_reg\[\d+\]|gLarge\.ram/gInfer\.q_reg\[\d+\]}] \ +set_max_delay -from [get_cells -regexp {gSmall\.regfile.*/.*|gLarge\.ram/gen.ram_reg.*/.*}] \ + -to [get_cells -regexp {gSmall\.do_reg\[\d+\]|gLarge\.ram/gen\.q_reg\[\d+\]}] \ -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {Ful_reg/C}]]], [get_property period [get_clocks -of_objects [get_pins {Avl_reg/C}]]])"] From f207751bfc3180644fb8b5d79936b2daa277f1ca Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Thu, 18 Jun 2026 23:33:40 +0200 Subject: [PATCH 04/18] fix variable direction for init mem file function --- regression.tcl | 8 ++++---- src/mem/mem.pkg.vhdl | 2 +- tools/poc.tcl | 2 ++ 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/regression.tcl b/regression.tcl index 69d6debd6..e33844540 100644 --- a/regression.tcl +++ b/regression.tcl @@ -83,25 +83,25 @@ configureOSVVM -stop 1 ; evaluateRegressionLevel $defaultStep $regressionLevels if {![file exists $::poc::localConfigurationPath] || $::regression::level == -1} { - ::poc::WriteLocalConfiguration + WriteLocalConfiguration } if {$::regression::level <= 0} { build ${root}/lib/OsvvmLibraries.pro [BuildName "${::poc::buildNamePrefix}OsvvmLibraries"] if {[checkForBuildErrors] || $::regression::executeSingleStep} { - return + return 1 } } if {$::regression::level <= 1} { build ${root}/PoC.pro [BuildName "${::poc::buildNamePrefix}PoC"] if {[checkForBuildErrors] || $::regression::executeSingleStep} { - return + return 1 } } if {$::regression::level <= 2} { build ${root}/tb/RunAllTests.pro [BuildName "${::poc::buildNamePrefix}RunAllTests"] if {[checkForRunErrors] || $::regression::executeSingleStep} { - return + return 1 } } diff --git a/src/mem/mem.pkg.vhdl b/src/mem/mem.pkg.vhdl index 05737b7b1..e548e1369 100644 --- a/src/mem/mem.pkg.vhdl +++ b/src/mem/mem.pkg.vhdl @@ -171,7 +171,7 @@ package body mem is variable CurrentLine : LINE; variable Good : boolean; variable TempWord : std_logic_vector((div_ceil(BitsPerMemoryLine, 4) * 4) - 1 downto 0); - variable Result : T_SLM(MemoryLines - 1 downto 0, BitsPerMemoryLine - 1 downto 0); + variable Result : T_SLM(0 to MemoryLines - 1, BitsPerMemoryLine - 1 downto 0); begin Result := (others => (others => ite(SIMULATION, 'U', '0'))); diff --git a/tools/poc.tcl b/tools/poc.tcl index 4e443b5ef..2ebee991b 100644 --- a/tools/poc.tcl +++ b/tools/poc.tcl @@ -182,6 +182,7 @@ Other tools: } proc WriteLocalConfiguration {} { + puts "Generate local configuration in '$::poc::localConfigurationPath' with working dir to root '$::poc::projectRoot'" set content "package local_configuration is\n" append content "\tconstant LOCAL_PROJECT_DIR : string := \"$::poc::projectRoot\";\n" append content "end package;\n" @@ -235,6 +236,7 @@ Other tools: namespace export exitScript namespace export configureOSVVM namespace export configurePoC + namespace export WriteLocalConfiguration namespace export checkForBuildErrors namespace export checkForRunErrors namespace export disabled From d029210540d46e49da7c8120ec51cbb4820ec576 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Fri, 19 Jun 2026 11:24:18 +0200 Subject: [PATCH 05/18] fix paths for local and project config file --- regression.tcl | 5 +++ src/build.pro | 4 +-- tools/poc.tcl | 96 ++++++++++++++++++++++++++------------------------ 3 files changed, 57 insertions(+), 48 deletions(-) diff --git a/regression.tcl b/regression.tcl index e33844540..1792b5241 100644 --- a/regression.tcl +++ b/regression.tcl @@ -86,6 +86,11 @@ if {![file exists $::poc::localConfigurationPath] || $::regression::level == -1} WriteLocalConfiguration } +puts "========================================" +puts "End of PoC configuration, start of build" +puts "========================================" +puts "" + if {$::regression::level <= 0} { build ${root}/lib/OsvvmLibraries.pro [BuildName "${::poc::buildNamePrefix}OsvvmLibraries"] if {[checkForBuildErrors] || $::regression::executeSingleStep} { diff --git a/src/build.pro b/src/build.pro index db70e8bbe..0c5085136 100644 --- a/src/build.pro +++ b/src/build.pro @@ -21,8 +21,8 @@ library PoC -analyze $::poc::projectConfigurationPath -analyze $::poc::localConfigurationPath +analyze $::poc::projectConfigurationFile +analyze $::poc::localConfigurationFile include ./common disabled ./misc/misc_ClockBuffer.vhdl diff --git a/tools/poc.tcl b/tools/poc.tcl index 2ebee991b..0cc183ae9 100644 --- a/tools/poc.tcl +++ b/tools/poc.tcl @@ -1,4 +1,5 @@ namespace eval ::poc { + variable putsPrefix "\[PoC\] " proc getEnv {var {default ""}} { if {[info exists ::env($var)]} { return $::env($var) @@ -11,11 +12,11 @@ namespace eval ::poc { variable boardName [getEnv BOARD "GENERIC"] variable buildNamePrefix "" - variable localConfigurationFolder "${projectRoot}/tb/common" - variable projectConfigurationFile "project_configuration_${::poc::boardName}.vhdl" - variable localConfigurationFile "local_configuration.vhdl" - variable projectConfigurationPath [file join $localConfigurationFolder "project_configuration_${::poc::boardName}.vhdl"] - variable localConfigurationPath [file join $localConfigurationFolder "local_configuration.vhdl"] + # Relative to the location of src/build.pro + variable localConfigurationFolder "../tb/common" + variable projectConfigurationFile "$localConfigurationFolder/project_configuration_${::poc::boardName}.vhdl" + variable localConfigurationFile "$localConfigurationFolder/local_configuration.vhdl" + variable localConfigurationPath "$projectRoot/src/$localConfigurationFolder/local_configuration.vhdl" variable disableExit 0 @@ -62,7 +63,7 @@ namespace eval ::poc { if {$i < [llength $args]} { set stopCount [lindex $args $i] } else { - puts "Option -stopCount requires an integer value." + puts "${::poc::putsPrefix}Option -stopCount requires an integer value." exitScript } } @@ -75,7 +76,7 @@ namespace eval ::poc { SetSaveWaves } default { - puts "ERROR: Unknown option $arg" + puts "${::poc::putsPrefix}ERROR: Unknown option $arg" exitScript } } @@ -102,16 +103,16 @@ namespace eval ::poc { } else { puts [format { -====================================== -Unknown simulator selected: %s - -Supported simulators: - - GHDL - - NVC - - Riviera-PRO -Other tools: - - Sigasi in VSCode -====================================== +${::poc::putsPrefix}====================================== +${::poc::putsPrefix}Unknown simulator selected: %s +${::poc::putsPrefix} +${::poc::putsPrefix}Supported simulators: +${::poc::putsPrefix} - GHDL +${::poc::putsPrefix} - NVC +${::poc::putsPrefix} - Riviera-PRO +${::poc::putsPrefix}Other tools: +${::poc::putsPrefix} - Sigasi in VSCode +${::poc::putsPrefix}====================================== } $::osvvm::ToolName] exitScript } @@ -149,7 +150,6 @@ Other tools: incr i if {$i < [llength $args]} { set ::poc::projectRoot [lindex $args $i] - set ::poc::localConfigurationFolder "${::poc::projectRoot}/tb/common" } } @@ -170,34 +170,37 @@ Other tools: } default { - puts "ERROR: Unknown option $arg" + puts "${::poc::putsPrefix}ERROR: Unknown option $arg" exitScript } } incr i } - set ::poc::projectConfigurationPath [file join ${::poc::localConfigurationFolder} ${::poc::projectConfigurationFile}] - set ::poc::localConfigurationPath [file join ${::poc::localConfigurationFolder} ${::poc::localConfigurationFile}] + puts "${::poc::putsPrefix}Relative to src/build.pro:" + puts "${::poc::putsPrefix}projectConfigurationFile is '$::poc::projectConfigurationFile'" + puts "${::poc::putsPrefix}localConfigurationFile is '$::poc::localConfigurationFile'" + + set ::poc::localConfigurationPath "$::poc::projectRoot/src/$::poc::localConfigurationFile" } proc WriteLocalConfiguration {} { - puts "Generate local configuration in '$::poc::localConfigurationPath' with working dir to root '$::poc::projectRoot'" + puts "${::poc::putsPrefix}Generate local configuration in '$::poc::localConfigurationFile' with working dir to root '$::poc::projectRoot'" set content "package local_configuration is\n" append content "\tconstant LOCAL_PROJECT_DIR : string := \"$::poc::projectRoot\";\n" append content "end package;\n" - set fileHandle [open $::poc::localConfigurationPath "w"] + set fileHandle [open "$::poc::projectRoot/src/$::poc::localConfigurationFile" "w"] puts -nonewline $fileHandle $content close $fileHandle } proc checkForBuildErrors {} { if {$::osvvm::AnalyzeErrorCount > 0} { - puts "ERROR: While building $::osvvm::LastBuildName" - puts "=====================================" - puts $::osvvm::BuildErrorInfo - puts "=====================================" + puts "${::poc::putsPrefix}ERROR: While building $::osvvm::LastBuildName" + puts "${::poc::putsPrefix}=====================================" + puts "${::poc::putsPrefix}$::osvvm::BuildErrorInfo" + puts "${::poc::putsPrefix}=====================================" exitScript return 1 @@ -207,18 +210,18 @@ Other tools: proc checkForRunErrors {} { if {$::osvvm::AnalyzeErrorCount > 0} { - puts "ERROR: While building $::osvvm::LastBuildName" - puts "=====================================" - puts $::osvvm::BuildErrorInfo - puts "=====================================" + puts "${::poc::putsPrefix}ERROR: While building $::osvvm::LastBuildName" + puts "${::poc::putsPrefix}=====================================" + puts "${::poc::putsPrefix}$::osvvm::BuildErrorInfo" + puts "${::poc::putsPrefix}=====================================" exitScript 2 return 1 } elseif {$::osvvm::SimulateErrorCount > 0} { - puts "ERROR: While simulating $::osvvm::TestCaseName" - puts "=====================================" - puts $::osvvm::BuildErrorInfo - puts "=====================================" + puts "${::poc::putsPrefix}ERROR: While simulating $::osvvm::TestCaseName" + puts "${::poc::putsPrefix}=====================================" + puts "${::poc::putsPrefix}$::osvvm::BuildErrorInfo" + puts "${::poc::putsPrefix}=====================================" exitScript 3 return 1 } @@ -227,10 +230,10 @@ Other tools: # New procedures for OSVVM's *.pro files proc disabled {args} { - puts "Disabled from analysis: $args" + puts "${::poc::putsPrefix}Disabled from analysis: $args" } proc duplicate {args} { - puts "Duplicate file: $args" + puts "${::poc::putsPrefix}Duplicate file: $args" } namespace export exitScript @@ -243,9 +246,10 @@ Other tools: namespace export duplicate } -puts "Loaded PoC extensions for OSVVM." +puts "${::poc::putsPrefix}Loaded tools/poc.tcl poc namespace." namespace eval ::regression { + variable putsPrefix "\[Regression\] " proc createRegressionLevels {args} { set map(clean) -1 set map(all) 0 @@ -270,7 +274,7 @@ namespace eval ::regression { return $map($step) } - puts "\[WARNING\] Unknown build level '$step', using 'all'." + puts "${::regression::putsPrefix}\[WARNING\] Unknown build level '$step', using 'all'." return 0 } @@ -297,20 +301,20 @@ namespace eval ::regression { } else { set buildConfigSource "default" set selectedStep $defaultStep - puts "\[REGRESSION INFO\] Undefined or unknown argument, using default settings." + puts "${::regression::putsPrefix}\[REGRESSION INFO\] Undefined or unknown argument, using default settings." } set ::regression::level [mapRegressionLevel $selectedStep $regressionLevels] # 3. output result - puts "==================================" - puts "Build configuration" - puts " Level: $::regression::level (set by $buildConfigSource)" - puts " Executing [expr {$::regression::executeSingleStep ? "only" : "starting from"}] step '$selectedStep'" - puts "==================================" + puts "${::regression::putsPrefix}==================================" + puts "${::regression::putsPrefix}Build configuration" + puts "${::regression::putsPrefix} Level: $::regression::level (set by $buildConfigSource)" + puts "${::regression::putsPrefix} Executing [expr {$::regression::executeSingleStep ? "only" : "starting from"}] step '$selectedStep'" + puts "${::regression::putsPrefix}==================================" } namespace export createRegressionLevels namespace export evaluateRegressionLevel } -puts "Loaded regression extensions." +puts "${::regression::putsPrefix}Loaded tools/poc.tcl regression namespace." From 6c886a9665082fe4cece5c18a52b0c39692dc909 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Fri, 19 Jun 2026 12:05:54 +0200 Subject: [PATCH 06/18] beautify print --- tools/poc.tcl | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/tools/poc.tcl b/tools/poc.tcl index 0cc183ae9..11cc366e5 100644 --- a/tools/poc.tcl +++ b/tools/poc.tcl @@ -178,8 +178,8 @@ ${::poc::putsPrefix}====================================== } puts "${::poc::putsPrefix}Relative to src/build.pro:" - puts "${::poc::putsPrefix}projectConfigurationFile is '$::poc::projectConfigurationFile'" - puts "${::poc::putsPrefix}localConfigurationFile is '$::poc::localConfigurationFile'" + puts "${::poc::putsPrefix} projectConfigurationFile is '$::poc::projectConfigurationFile'" + puts "${::poc::putsPrefix} localConfigurationFile is '$::poc::localConfigurationFile'" set ::poc::localConfigurationPath "$::poc::projectRoot/src/$::poc::localConfigurationFile" } @@ -306,11 +306,9 @@ namespace eval ::regression { set ::regression::level [mapRegressionLevel $selectedStep $regressionLevels] # 3. output result - puts "${::regression::putsPrefix}==================================" puts "${::regression::putsPrefix}Build configuration" puts "${::regression::putsPrefix} Level: $::regression::level (set by $buildConfigSource)" puts "${::regression::putsPrefix} Executing [expr {$::regression::executeSingleStep ? "only" : "starting from"}] step '$selectedStep'" - puts "${::regression::putsPrefix}==================================" } namespace export createRegressionLevels From 7a4cec6d2859199b8e8c0b94e3b366f73873ed42 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 08:22:46 +0200 Subject: [PATCH 07/18] FILL_STATE vs. FULL_STATE vs. FSTATE. --- docs/IPCores/fifo/index.rst | 2 +- src/bus/axi4/axi4_FIFO_CDC.vhdl | 50 +++++----- src/bus/axi4lite/axi4lite_FIFO_CDC.vhdl | 24 ++--- src/bus/axi4lite/axi4lite_UART.vhdl | 14 +-- src/bus/axi4stream/axi4stream_FIFO_CDC.vhdl | 48 ++++----- src/fifo/README.md | 2 +- src/fifo/fifo.pkg.vhdl | 24 ++--- src/fifo/fifo_ic_got.vhdl | 104 ++++++++++---------- src/io/uart/uart.pkg.vhdl | 8 +- src/io/uart/uart_FIFO.vhdl | 42 ++++---- src/xil/reconfig/reconfig_ICAP_Wrapper.vhdl | 102 +++++++++---------- 11 files changed, 210 insertions(+), 210 deletions(-) diff --git a/docs/IPCores/fifo/index.rst b/docs/IPCores/fifo/index.rst index 2a41db7a2..7a8602486 100644 --- a/docs/IPCores/fifo/index.rst +++ b/docs/IPCores/fifo/index.rst @@ -16,7 +16,7 @@ is available on the output. Asserting the `got`-input, acknoledge the processing the current output signals and moves the read-pointer to the next value, if available. All FIFOs implement a bidirectional flow control (`put`/`full` and `valid`/`got`). -Each FIFO also offers a EmptyState (write-side) and FullState (read-side) to indicate +Each FIFO also offers a EmptyState (write-side) and FillState (read-side) to indicate the current fill-state. The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent diff --git a/src/bus/axi4/axi4_FIFO_CDC.vhdl b/src/bus/axi4/axi4_FIFO_CDC.vhdl index dac1c0d96..4bfd8f462 100644 --- a/src/bus/axi4/axi4_FIFO_CDC.vhdl +++ b/src/bus/axi4/axi4_FIFO_CDC.vhdl @@ -108,20 +108,20 @@ architecture rtl of axi4_FIFO_CDC is constant B_POS : natural := 4; constant BIT_VEC : positive_vector := ( - AW_POS => isum(W_Addr_BIT_VEC), - AR_POS => isum(R_Addr_BIT_VEC), - W_POS => isum(W_BIT_VEC), - R_POS => isum(R_BIT_VEC), - B_POS => isum(B_BIT_VEC) - ); + AW_POS => isum(W_Addr_BIT_VEC), + AR_POS => isum(R_Addr_BIT_VEC), + W_POS => isum(W_BIT_VEC), + R_POS => isum(R_BIT_VEC), + B_POS => isum(B_BIT_VEC) + ); constant MIN_DEPTH : positive_vector := ( - AW_POS => FRAMES, - AR_POS => FRAMES, - W_POS => FRAMES * FRAME_DEPTH, - R_POS => FRAMES * FRAME_DEPTH, - B_POS => FRAMES - ); + AW_POS => FRAMES, + AR_POS => FRAMES, + W_POS => FRAMES * FRAME_DEPTH, + R_POS => FRAMES * FRAME_DEPTH, + B_POS => FRAMES + ); signal In_Ready_vec : std_logic_vector(0 to 4); signal In_Valid_vec : std_logic_vector(0 to 4); @@ -130,8 +130,6 @@ architecture rtl of axi4_FIFO_CDC is signal DataFIFO_DataIn : std_logic_vector(isum(BIT_VEC) -1 downto 0); signal DataFIFO_DataOut : std_logic_vector(isum(BIT_VEC) -1 downto 0); - - begin -----INPUT In_S2M.AWReady <= In_Ready_vec(AW_POS); @@ -370,20 +368,20 @@ begin ) port map ( -- Writing Interface - clk_wr => ite(i<3,In_Clock,Out_Clock), - rst_wr => ite(i<3,In_Reset,Out_Reset), - put => DataFIFO_put, - din => DataFIFO_DataIn_i, - full => DataFIFO_Full, - estate_wr => open, + Write_Clock => ite(i<3,In_Clock,Out_Clock), + Write_Reset => ite(i<3,In_Reset,Out_Reset), + Write_Put => DataFIFO_put, + Write_DataIn => DataFIFO_DataIn_i, + Write_Full => DataFIFO_Full, + Write_EmptyState => open, -- Reading Interface - clk_rd => ite(i<3,Out_Clock,In_Clock), - rst_rd => ite(i<3,Out_Reset,In_Reset), - got => DataFIFO_got, - dout => DataFIFO_DataOut_i, - valid => DataFIFO_Valid, - fstate_rd => open + Read_Clock => ite(i<3,Out_Clock,In_Clock), + Read_Reset => ite(i<3,Out_Reset,In_Reset), + Read_Valid => DataFIFO_Valid, + Read_DataOut => DataFIFO_DataOut_i, + Read_Got => DataFIFO_got, + Read_FillState => open ); end generate; diff --git a/src/bus/axi4lite/axi4lite_FIFO_CDC.vhdl b/src/bus/axi4lite/axi4lite_FIFO_CDC.vhdl index 10db87dfa..d1c542b5c 100644 --- a/src/bus/axi4lite/axi4lite_FIFO_CDC.vhdl +++ b/src/bus/axi4lite/axi4lite_FIFO_CDC.vhdl @@ -227,20 +227,20 @@ begin ) port map ( -- Writing Interface - clk_wr => ite(i<3,In_Clock,Out_Clock), - rst_wr => ite(i<3,In_Reset,Out_Reset), - put => DataFIFO_put, - din => DataFIFO_DataIn_i, - full => DataFIFO_Full, - estate_wr => open, + Write_Clock => ite(i<3,In_Clock,Out_Clock), + Write_Reset => ite(i<3,In_Reset,Out_Reset), + Write_Put => DataFIFO_put, + Write_DataIn => DataFIFO_DataIn_i, + Write_Full => DataFIFO_Full, + Write_EmptyState => open, -- Reading Interface - clk_rd => ite(i<3,Out_Clock,In_Clock), - rst_rd => ite(i<3,Out_Reset,In_Reset), - got => DataFIFO_got, - dout => DataFIFO_DataOut_i, - valid => DataFIFO_Valid, - fstate_rd => open + Read_Clock => ite(i<3,Out_Clock,In_Clock), + Read_Reset => ite(i<3,Out_Reset,In_Reset), + Read_Got => DataFIFO_got, + Read_DataOut => DataFIFO_DataOut_i, + Read_Valid => DataFIFO_Valid, + Read_FillState => open ); diff --git a/src/bus/axi4lite/axi4lite_UART.vhdl b/src/bus/axi4lite/axi4lite_UART.vhdl index ee4c00d27..5226887a5 100644 --- a/src/bus/axi4lite/axi4lite_UART.vhdl +++ b/src/bus/axi4lite/axi4lite_UART.vhdl @@ -76,7 +76,7 @@ end entity; architecture rtl of axi4lite_UART is constant TX_EMPTY_STATE_BITS : natural := 4; - constant RX_FULL_STATE_BITS : natural := 4; + constant RX_FILL_STATE_BITS : natural := 4; constant Reg_config : T_AXI4_Register_Vector := ( to_AXI4_Register(Name => "Rx", Address => 32x"00", RegisterMode => ReadOnly_NotRegistered, Init_Value => x"00000000"), @@ -120,7 +120,7 @@ architecture rtl of axi4lite_UART is signal Control_InterruptEnable : std_logic; signal Status_TX_EmptyState : std_logic_vector(imax(0, TX_EMPTY_STATE_BITS - 1) downto 0); - signal Status_RX_FullState : std_logic_vector(imax(0, RX_FULL_STATE_BITS - 1) downto 0); + signal Status_RX_FillState : std_logic_vector(imax(0, RX_FILL_STATE_BITS - 1) downto 0); begin Reg : entity work.axi4lite_Register generic map( @@ -187,10 +187,10 @@ begin ADD_INPUT_SYNCHRONIZERS => ADD_INPUT_SYNCHRONIZERS, -- Buffer Dimensioning - TX_MIN_DEPTH => TX_FIFO_DEPTH, - TX_ESTATE_BITS => TX_EMPTY_STATE_BITS, - RX_MIN_DEPTH => RX_FIFO_DEPTH, - RX_FSTATE_BITS => RX_FULL_STATE_BITS, + TX_MIN_DEPTH => TX_FIFO_DEPTH, + TX_EMPTY_STATE_BITS => TX_EMPTY_STATE_BITS, + RX_MIN_DEPTH => RX_FIFO_DEPTH, + RX_FILL_STATE_BITS => RX_FILL_STATE_BITS, -- Flow Control FLOWCONTROL => FLOWCONTROL, @@ -211,7 +211,7 @@ begin RX_Valid => Status_RX_Valid, RX_Data => RX_Data, RX_Got => RX_Got, - RX_FullState => Status_RX_FullState, + RX_FillState => Status_RX_FillState, RX_Overflow => RX_OverFlow, RXFIFO_Full => Status_RX_Full, RXFIFO_Reset => Control_RX_Reset, diff --git a/src/bus/axi4stream/axi4stream_FIFO_CDC.vhdl b/src/bus/axi4stream/axi4stream_FIFO_CDC.vhdl index 0803d2e15..a5c0012fa 100644 --- a/src/bus/axi4stream/axi4stream_FIFO_CDC.vhdl +++ b/src/bus/axi4stream/axi4stream_FIFO_CDC.vhdl @@ -175,20 +175,20 @@ begin ) port map ( -- Writing Interface - clk_wr => In_Clock, - rst_wr => In_Reset, - put => DataFIFO_put, - din => DataFIFO_DataIn(ite(USER_IS_DYNAMIC, isum(FIFO_BIT_VEC), isum(FIFO_BIT_VEC) - USER_BITS) -1 downto 0), - full => DataFIFO_Full, - estate_wr => open, + Write_Clock => In_Clock, + Write_Reset => In_Reset, + Write_Put => DataFIFO_put, + Write_DataIn => DataFIFO_DataIn(ite(USER_IS_DYNAMIC, isum(FIFO_BIT_VEC), isum(FIFO_BIT_VEC) - USER_BITS) -1 downto 0), + Write_Full => DataFIFO_Full, + Write_EmptyState => open, -- Reading Interface - clk_rd => Out_Clock, - rst_rd => Out_Reset, - got => DataFIFO_got, - dout => DataFIFO_DataOut(ite(USER_IS_DYNAMIC, isum(FIFO_BIT_VEC), isum(FIFO_BIT_VEC) - USER_BITS) -1 downto 0), - valid => DataFIFO_Valid, - fstate_rd => open + Read_Clock => Out_Clock, + Read_Reset => Out_Reset, + Read_Got => DataFIFO_got, + Read_DataOut => DataFIFO_DataOut(ite(USER_IS_DYNAMIC, isum(FIFO_BIT_VEC), isum(FIFO_BIT_VEC) - USER_BITS) -1 downto 0), + Read_Valid => DataFIFO_Valid, + Read_FillState => open ); Out_M2S <= Out_M2S_i; @@ -229,20 +229,20 @@ begin ) port map ( -- Writing Interface - clk_wr => In_Clock, - rst_wr => In_Reset, - put => MetaFIFO_put, - din => Meta_In, - full => MetaFIFO_Full, - estate_wr => open, + Write_Clock => In_Clock, + Write_Reset => In_Reset, + Write_Put => MetaFIFO_put, + Write_DataIn => Meta_In, + Write_Full => MetaFIFO_Full, + Write_EmptyState => open, -- Reading Interface - clk_rd => Out_Clock, - rst_rd => Out_Reset, - got => Out_M2S_i.Valid and Out_M2S_i.Last and Out_S2M.Ready, - dout => Meta_Out, - valid => open, - fstate_rd => open + Read_Clock => Out_Clock, + Read_Reset => Out_Reset, + Read_Got => Out_M2S_i.Valid and Out_M2S_i.Last and Out_S2M.Ready, + Read_DataOut => Meta_Out, + Read_Valid => open, + Read_FillState => open ); else generate MetaFIFO_Full <= '0'; diff --git a/src/fifo/README.md b/src/fifo/README.md index dc6c67ad2..91f307b43 100644 --- a/src/fifo/README.md +++ b/src/fifo/README.md @@ -15,7 +15,7 @@ is available on the output. Asserting the `got`-input, acknoledge the processing the current output signals and moves the read-pointer to the next value, if available. All FIFOs implement a bidirectional flow control (`put`/`full` and `valid`/`got`). -Each FIFO also offers a EmptyState (write-side) and FullState (read-side) to indicate +Each FIFO also offers a EmptyState (write-side) and FillState (read-side) to indicate the current fill-state. The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent diff --git a/src/fifo/fifo.pkg.vhdl b/src/fifo/fifo.pkg.vhdl index d6eaf9f96..12629ff61 100644 --- a/src/fifo/fifo.pkg.vhdl +++ b/src/fifo/fifo.pkg.vhdl @@ -125,20 +125,20 @@ package fifo is ); port ( -- Write Interface - clk_wr : in std_logic; - rst_wr : in std_logic; - put : in std_logic; - din : in std_logic_vector(DATA_BITS - 1 downto 0); - full : out std_logic; - estate_wr : out std_logic_vector(imax(EMPTY_STATE_BITS - 1, 0) downto 0); + Write_Clock : in std_logic; + Write_Reset : in std_logic; + Write_Put : in std_logic; + Write_DataIn : in std_logic_vector(DATA_BITS - 1 downto 0); + Write_Full : out std_logic; + Write_EmptyState : out std_logic_vector(imax(EMPTY_STATE_BITS - 1, 0) downto 0); -- Read Interface - clk_rd : in std_logic; - rst_rd : in std_logic; - got : in std_logic; - valid : out std_logic; - dout : out std_logic_vector(DATA_BITS - 1 downto 0); - fstate_rd : out std_logic_vector(imax(FILL_STATE_BITS - 1, 0) downto 0) + Read_Clock : in std_logic; + Read_Reset : in std_logic; + Read_Got : in std_logic; + Read_Valid : out std_logic; + Read_DataOut : out std_logic_vector(DATA_BITS - 1 downto 0); + Read_FillState : out std_logic_vector(imax(FILL_STATE_BITS - 1, 0) downto 0) ); end component; diff --git a/src/fifo/fifo_ic_got.vhdl b/src/fifo/fifo_ic_got.vhdl index 16be0edb1..88d80d987 100644 --- a/src/fifo/fifo_ic_got.vhdl +++ b/src/fifo/fifo_ic_got.vhdl @@ -83,20 +83,20 @@ entity fifo_ic_got is ); port ( -- Write Interface - clk_wr : in std_logic; - rst_wr : in std_logic; - put : in std_logic; - din : in std_logic_vector(DATA_BITS-1 downto 0); - full : out std_logic; - estate_wr : out std_logic_vector(imax(EMPTY_STATE_BITS-1, 0) downto 0); + Write_Clock : in std_logic; + Write_Reset : in std_logic; + Write_Put : in std_logic; + Write_DataIn : in std_logic_vector(DATA_BITS-1 downto 0); + Write_Full : out std_logic; + Write_EmptyState : out std_logic_vector(imax(EMPTY_STATE_BITS-1, 0) downto 0); -- Read Interface - clk_rd : in std_logic; - rst_rd : in std_logic; - got : in std_logic; - valid : out std_logic; - dout : out std_logic_vector(DATA_BITS-1 downto 0); - fstate_rd : out std_logic_vector(imax(FILL_STATE_BITS-1, 0) downto 0) + Read_Clock : in std_logic; + Read_Reset : in std_logic; + Read_Valid : out std_logic; + Read_DataOut : out std_logic_vector(DATA_BITS-1 downto 0); + Read_Got : in std_logic; + Read_FillState : out std_logic_vector(imax(FILL_STATE_BITS-1, 0) downto 0) ); end entity; @@ -141,10 +141,10 @@ begin blkIP: block signal Cnt : unsigned(AN-1 downto 0) := to_unsigned(1, AN); begin - process(clk_wr) + process(Write_Clock) begin - if rising_edge(clk_wr) then - if rst_wr = '1' then + if rising_edge(Write_Clock) then + if Write_Reset = '1' then Cnt <= to_unsigned(1, AN); elsif puti = '1' then Cnt <= Cnt + 1; @@ -155,10 +155,10 @@ begin end block blkIP; -- Update Write Pointer upon puti - process(clk_wr) + process(Write_Clock) begin - if rising_edge(clk_wr) then - if rst_wr = '1' then + if rising_edge(Write_Clock) then + if Write_Reset = '1' then IP0 <= (others => '0'); Ful <= '0'; else @@ -180,23 +180,23 @@ begin end if; end if; end process; - puti <= put and not Ful; - full <= Ful; + puti <= Write_Put and not Ful; + Write_Full <= Ful; - di <= din; + di <= Write_DataIn; wa <= unsigned(IP0(ADDRESS_BITS-1 downto 0)); -- write pointer needs to be delayed by one CC to asure that data -- is fully stored before giving it free to the other side. -- Problem when clk_rd > 2* clk_wr - IP0_d <= IP0 when rising_edge(clk_wr); + IP0_d <= IP0 when rising_edge(Write_Clock); Read_pointer_sync : entity work.sync_Bits generic map( BITS => AN, REGISTER_OUTPUT => false ) port map( - Clock => clk_rd, + Clock => Read_Clock, Input => IP0_d, Output => IPc ); @@ -207,10 +207,10 @@ begin blkOP: block signal Cnt : unsigned(AN-1 downto 0) := to_unsigned(1, AN); begin - process(clk_rd) + process(Read_Clock) begin - if rising_edge(clk_rd) then - if rst_rd = '1' then + if rising_edge(Read_Clock) then + if Read_Reset = '1' then Cnt <= to_unsigned(1, AN); elsif geti = '1' then Cnt <= Cnt + 1; @@ -220,10 +220,10 @@ begin OP1 <= std_logic_vector(Cnt(ADDRESS_BITS) & (Cnt(ADDRESS_BITS-1 downto 0) xor ('0' & Cnt(ADDRESS_BITS-1 downto 1)))); end block blkOP; - process(clk_rd) + process(Read_Clock) begin - if rising_edge(clk_rd) then - if rst_rd = '1' then + if rising_edge(Read_Clock) then + if Read_Reset = '1' then OP0 <= (others => '0'); Avl <= '0'; Vld <= '0'; @@ -257,14 +257,14 @@ begin -- read pointer needs to be delayed by one CC to asure that data -- is read out before giving it free to the other side -- Problem when clk_wr > 2* clk_rd - OP0_d <= OP0 when rising_edge(clk_rd); + OP0_d <= OP0 when rising_edge(Read_Clock); Write_pointer_sync : entity work.sync_Bits generic map( BITS => AN, REGISTER_OUTPUT => false ) port map( - Clock => clk_wr, + Clock => Write_Clock, Input => OP0_d, Output => OPc ); @@ -276,18 +276,18 @@ begin -- register in that case. ----------------------------------------------------------------------------- genRegN: if DATA_REG or not OUTPUT_REG generate - goti <= got; - dout <= do; - valid <= Vld; + goti <= Read_Got; + Read_DataOut <= do; + Read_Valid <= Vld; end generate genRegN; genRegY: if (not DATA_REG) and OUTPUT_REG generate signal Buf : std_logic_vector(DATA_BITS-1 downto 0) := (others => '-'); signal VldB : std_logic := '0'; begin - process(clk_rd) + process(Read_Clock) begin - if rising_edge(clk_rd) then - if rst_rd = '1' then + if rising_edge(Read_Clock) then + if Read_Reset = '1' then Buf <= (others => '-'); VldB <= '0'; elsif goti = '1' then @@ -296,9 +296,9 @@ begin end if; end if; end process; - goti <= not VldB or got; - dout <= Buf; - valid <= VldB; + goti <= not VldB or Read_Got; + Read_DataOut <= Buf; + Read_Valid <= VldB; end generate genRegY; ----------------------------------------------------------------------------- @@ -309,11 +309,11 @@ begin signal d : unsigned(ADDRESS_BITS-1 downto 0); begin d <= gray2bin(OPc(ADDRESS_BITS-1 downto 0)) + not gray2bin(IP0(ADDRESS_BITS-1 downto 0)); - estate_wr <= (others => '0') when Ful = '1' else + Write_EmptyState <= (others => '0') when Ful = '1' else std_logic_vector(d(d'left downto d'left-EMPTY_STATE_BITS+1)); end generate gEstateWr; gNoEstateWr: if EMPTY_STATE_BITS = 0 generate - estate_wr <= "X"; + Write_EmptyState <= "X"; end generate gNoEstateWr; -- Read Clock Domain @@ -321,11 +321,11 @@ begin signal d : unsigned(ADDRESS_BITS-1 downto 0); begin d <= gray2bin(IPc(ADDRESS_BITS-1 downto 0)) + not gray2bin(OP0(ADDRESS_BITS-1 downto 0)); - fstate_rd <= (others => '0') when Avl = '0' else + Read_FillState <= (others => '0') when Avl = '0' else std_logic_vector(d(d'left downto d'left-FILL_STATE_BITS+1)); end generate gFstateRd; gNoFstateRd: if FILL_STATE_BITS = 0 generate - fstate_rd <= "X"; + Read_FillState <= "X"; end generate gNoFstateRd; ----------------------------------------------------------------------------- @@ -338,8 +338,8 @@ begin DATA_BITS => DATA_BITS ) port map ( - Write_Clock => clk_wr, - Read_Clock => clk_rd, + Write_Clock => Write_Clock, + Read_Clock => Read_Clock, Write_ClockEnable => '1', Read_ClockEnable => geti, Write_WriteEnable => puti, @@ -367,11 +367,11 @@ begin begin -- Memory State - process(clk_wr) + process(Write_Clock) begin - if rising_edge(clk_wr) then + if rising_edge(Write_Clock) then --synthesis translate_off - if SIMULATION and (rst_wr = '1') then + if SIMULATION and (Write_Reset = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on @@ -385,10 +385,10 @@ begin end process; -- Memory Output - process (clk_rd) + process (Read_Clock) begin -- process - if rising_edge(clk_rd) then - if SIMULATION and (rst_rd = '1') then + if rising_edge(Read_Clock) then + if SIMULATION and (Read_Reset = '1') then do <= (others => 'U'); elsif geti = '1' then if Is_X(std_logic_vector(ra)) then diff --git a/src/io/uart/uart.pkg.vhdl b/src/io/uart/uart.pkg.vhdl index fbb95a4f9..7fb7f471e 100644 --- a/src/io/uart/uart.pkg.vhdl +++ b/src/io/uart/uart.pkg.vhdl @@ -128,9 +128,9 @@ package uart is PARITY_ERROR_IDENTIFIER : std_logic_vector(7 downto 0) := 8x"0"; ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; TX_MIN_DEPTH : positive := 16; - TX_ESTATE_BITS : natural := 0; + TX_EMPTY_STATE_BITS : natural := 0; RX_MIN_DEPTH : positive := 16; - RX_FSTATE_BITS : natural := 0; + RX_FILL_STATE_BITS : natural := 0; FLOWCTRL_XON_THRESHOLD : real := 0.0625; FLOWCTRL_XOFF_THRESHOLD : real := 0.75; FLOWCONTROL : T_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE; @@ -144,14 +144,14 @@ package uart is TX_Put : in std_logic; TX_Data : in std_logic_vector(7 downto 0); TX_Full : out std_logic; - TX_EmptyState : out std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0); + TX_EmptyState : out std_logic_vector(imax(0, TX_EMPTY_STATE_BITS-1) downto 0); TXFIFO_Reset : in std_logic; TXFIFO_Empty : out std_logic; RX_Valid : out std_logic; RX_Data : out std_logic_vector(7 downto 0); RX_Got : in std_logic; - RX_FullState : out std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); + RX_FillState : out std_logic_vector(imax(0, RX_FILL_STATE_BITS-1) downto 0); RX_Overflow : out std_logic; RXFIFO_Full : out std_logic; RXFIFO_Reset : in std_logic; diff --git a/src/io/uart/uart_FIFO.vhdl b/src/io/uart/uart_FIFO.vhdl index 4c42501ee..c2b3ce503 100644 --- a/src/io/uart/uart_FIFO.vhdl +++ b/src/io/uart/uart_FIFO.vhdl @@ -61,9 +61,9 @@ entity uart_FIFO is -- Buffer Dimensioning TX_MIN_DEPTH : positive := 16; - TX_ESTATE_BITS : natural := 0; -- XXX: adjust to FIFO naming + TX_EMPTY_STATE_BITS : natural := 0; -- XXX: adjust to FIFO naming RX_MIN_DEPTH : positive := 16; - RX_FSTATE_BITS : natural := 0; + RX_FILL_STATE_BITS : natural := 0; FLOWCTRL_XON_THRESHOLD : real := 0.0625; FLOWCTRL_XOFF_THRESHOLD : real := 0.75; @@ -82,14 +82,14 @@ entity uart_FIFO is TX_Put : in std_logic; TX_Data : in std_logic_vector(7 downto 0); TX_Full : out std_logic; - TX_EmptyState : out std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0); + TX_EmptyState : out std_logic_vector(imax(0, TX_EMPTY_STATE_BITS-1) downto 0); TXFIFO_Reset : in std_logic; TXFIFO_Empty : out std_logic; RX_Valid : out std_logic; RX_Data : out std_logic_vector(7 downto 0); RX_Got : in std_logic; - RX_FullState : out std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); -- XXX: FullState or FillState ? + RX_FillState : out std_logic_vector(imax(0, RX_FILL_STATE_BITS-1) downto 0); RX_Overflow : out std_logic; RXFIFO_Full : out std_logic; RXFIFO_Reset : in std_logic; @@ -117,7 +117,7 @@ architecture rtl of uart_FIFO is signal TXFIFO_Data : T_SLV_8; signal RXFIFO_Full_int : std_logic; - signal RX_FullState_int : std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); + signal RX_FillState_int : std_logic_vector(imax(0, RX_FILL_STATE_BITS-1) downto 0); signal TXUART_Full : std_logic; signal RXUART_Strobe : std_logic; @@ -144,7 +144,7 @@ begin DATA_REG => TRUE, -- Store Data Content in Registers STATE_REG => FALSE, -- Registered Full/Empty Indicators OUTPUT_REG => FALSE, -- Registered FIFO Output - EMPTY_STATE_BITS => TX_ESTATE_BITS, -- Empty State Bits + EMPTY_STATE_BITS => TX_EMPTY_STATE_BITS, -- Empty State Bits FILL_STATE_BITS => 0 -- Full State Bits ) port map ( @@ -169,7 +169,7 @@ begin STATE_REG => FALSE, -- Registered Full/Empty Indicators OUTPUT_REG => FALSE, -- Registered FIFO Output EMPTY_STATE_BITS => 0, -- Empty State Bits - FILL_STATE_BITS => RX_FSTATE_BITS -- Full State Bits + FILL_STATE_BITS => RX_FILL_STATE_BITS -- Full State Bits ) port map ( Reset => Reset or RXFIFO_Reset, @@ -182,11 +182,11 @@ begin Valid => RX_Valid, DataOut => RX_Data, Got => RX_Got, - FillState => RX_FullState_int + FillState => RX_FillState_int ); RXFIFO_Full <= RXFIFO_Full_int; - RX_FullState <= RX_FullState_int; + RX_FillState <= RX_FillState_int; TXFIFO_Empty <= NOT TXFIFO_Valid; @@ -207,8 +207,8 @@ begin -- Software Flow Control -- =========================================================================== genSWFC : if FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF generate - constant XON_TRIG : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FSTATE_BITS)); - constant XOFF_TRIG : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FSTATE_BITS)); + constant XON_TRIG : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FILL_STATE_BITS)); + constant XOFF_TRIG : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FILL_STATE_BITS)); signal send_xoff : std_logic; signal send_xon : std_logic; @@ -217,21 +217,21 @@ begin signal clr_xoff_transmitted : std_logic; signal discard_user_tx : std_logic; signal discard_user_rx : std_logic; - signal RxFifo_FullState : integer := 0; -- receive fifo full_state + signal RxFifo_FillState : integer := 0; -- receive fifo fill_state -- registers signal xoff_transmitted : std_logic := '0'; signal transmit_enable : std_logic := '1'; begin - RxFifo_FullState <= to_integer(unsigned(RX_FullState_int)); + RxFifo_FillState <= to_integer(unsigned(RX_FillState_int)); --assert false report"FLOWCONTROL=" & T_IO_UART_FLOWCONTROL_KIND'image(FLOWCONTROL) & " is currently not supported!" severity failure; -- send XOFF only once when fill state goes above trigger level - send_xoff <= not xoff_transmitted when (RxFifo_FullState >= XOFF_TRIG) else '0'; - set_xoff_transmitted <= (not TXUART_Full) when (RxFifo_FullState >= XOFF_TRIG) else '0'; + send_xoff <= not xoff_transmitted when (RxFifo_FillState >= XOFF_TRIG) else '0'; + set_xoff_transmitted <= (not TXUART_Full) when (RxFifo_FillState >= XOFF_TRIG) else '0'; -- send XON only once when receive FIFO is almost empty - send_xon <= xoff_transmitted when (RxFifo_FullState <= XON_TRIG) else '0'; - clr_xoff_transmitted <= (not TXUART_Full) when (RxFifo_FullState <= XON_TRIG) else '0'; + send_xon <= xoff_transmitted when (RxFifo_FillState <= XON_TRIG) else '0'; + clr_xoff_transmitted <= (not TXUART_Full) when (RxFifo_FillState <= XON_TRIG) else '0'; -- discard any user supplied XON/XOFF discard_user_tx <= '1' when (TXFIFO_Data = SWFC_XON_CHAR) or (TXFIFO_Data = SWFC_XOFF_CHAR) else '0'; @@ -274,8 +274,8 @@ begin -- Hardware Flow Control -- =========================================================================== genHWFC1 : if FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS generate - constant RX_FSTATE_UPPER_LIMIT : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FSTATE_BITS)); - constant RX_FSTATE_LOWER_LIMIT : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FSTATE_BITS)); + constant RX_FSTATE_UPPER_LIMIT : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FILL_STATE_BITS)); + constant RX_FSTATE_LOWER_LIMIT : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FILL_STATE_BITS)); begin --assert false report"FLOWCONTROL=" & T_IO_UART_FLOWCONTROL_KIND'image(FLOWCONTROL) & " is currently not supported!" severity failure; @@ -293,9 +293,9 @@ begin if TXUART_Full = '0' then if Reset = '1' then UART_RTS<='1'; - elsif (to_integer(unsigned(RX_FullState_int)) >= RX_FSTATE_UPPER_LIMIT) then + elsif (to_integer(unsigned(RX_FillState_int)) >= RX_FSTATE_UPPER_LIMIT) then UART_RTS<='0'; - elsif (to_integer(unsigned(RX_FullState_int)) <= RX_FSTATE_LOWER_LIMIT) then + elsif (to_integer(unsigned(RX_FillState_int)) <= RX_FSTATE_LOWER_LIMIT) then UART_RTS<='1'; end if; end if; diff --git a/src/xil/reconfig/reconfig_ICAP_Wrapper.vhdl b/src/xil/reconfig/reconfig_ICAP_Wrapper.vhdl index 1146e6986..6cef95f52 100644 --- a/src/xil/reconfig/reconfig_ICAP_Wrapper.vhdl +++ b/src/xil/reconfig/reconfig_ICAP_Wrapper.vhdl @@ -38,28 +38,28 @@ use work.utils.all; entity reconfig_ICAP_Wrapper is generic ( - MIN_DEPTH_OUT : positive := 256; - MIN_DEPTH_IN : positive := 256 + INPUT_FIFO_DEPTH : positive := 256; + OUTPUT_FIFO_DEPTH : positive := 256 ); port ( - Clock : in std_logic; - Reset : in std_logic; - ICAP_Clock : in std_logic; -- clock signal for ICAP, max 100 MHz (double check with manual) + Clock : in std_logic; + Reset : in std_logic; + ICAP_Clock : in std_logic; -- clock signal for ICAP, max 100 MHz (double check with manual) - icap_busy : out std_logic; -- the ICAP is processing the data - icap_readback : out std_logic; -- high during a readback - icap_partial_res: out std_logic; -- high during reconfiguration + ICAP_Busy : out std_logic; -- the ICAP is processing the data + ICAP_Readback : out std_logic; -- high during a readback + ICAP_Partial_res : out std_logic; -- high during reconfiguration -- data in - write_put : in std_logic; - write_full : out std_logic; - write_data : in std_logic_vector(31 downto 0); - write_done : in std_logic; -- high pulse/edge after all data was written + Write_Put : in std_logic; + Write_Data : in std_logic_vector(31 downto 0); + Write_Full : out std_logic; + Write_Done : in std_logic; -- high pulse/edge after all data was written -- data out - read_got : in std_logic; - read_valid : out std_logic; - read_data : out std_logic_vector(31 downto 0) + Read_Valid : out std_logic; + Read_Data : out std_logic_vector(31 downto 0); + Read_Got : in std_logic ); end entity; @@ -99,12 +99,12 @@ architecture Behavioral of reconfig_ICAP_Wrapper is signal fsm_ready : std_logic; signal fsm_ready_d : std_logic; begin - write_done_d <= write_done when rising_edge(Clock); - write_done_edge <= to_sl(write_done = '1' and write_done_d = '0'); + write_done_d <= Write_Done when rising_edge(Clock); + write_done_edge <= to_sl(Write_Done = '1' and write_done_d = '0'); - icap_busy <= not fsm_status_clk(3); - icap_readback <= fsm_status_clk(1); - icap_partial_res <= fsm_status_clk(0); + ICAP_Busy <= not fsm_status_clk(3); + ICAP_Readback <= fsm_status_clk(1); + ICAP_Partial_res <= fsm_status_clk(0); fsm_ready <= fsm_status(3); fsm_ready_d <= fsm_ready when rising_edge(ICAP_Clock); @@ -131,25 +131,25 @@ begin -- reader: core fifo_in: entity work.fifo_ic_got generic map( - DATA_BITS => 32, - MIN_DEPTH => MIN_DEPTH_IN, - OUTPUT_REG => false, + DATA_BITS => 32, + MIN_DEPTH => INPUT_FIFO_DEPTH, + OUTPUT_REG => false, FILL_STATE_BITS => STATE_BITS ) port map( - clk_wr => Clock, - rst_wr => Reset, - put => write_put, - din => write_data, - full => write_full, - estate_wr => open, - - clk_rd => ICAP_Clock, - rst_rd => reset_icap, - got => in_data_rden, - valid => in_data_valid, - dout => in_data, - fstate_rd => in_data_fill_state + Write_Clock => Clock, + Write_Reset => Reset, + Write_Put => Write_Put, + Write_DataIn => Write_Data, + Write_Full => Write_Full, + Write_EmptyState => open, + + Read_Clock => ICAP_Clock, + Read_Reset => reset_icap, + Read_Valid => in_data_valid, + Read_DataOut => in_data, + Read_Got => in_data_rden, + Read_FillState => in_data_fill_state ); -- sync data from this core to the pci bus @@ -157,22 +157,24 @@ begin -- reader: pci fifo_out: entity work.fifo_ic_got generic map( - DATA_BITS => 32, - MIN_DEPTH => MIN_DEPTH_OUT, - OUTPUT_REG => false + DATA_BITS => 32, + MIN_DEPTH => OUTPUT_FIFO_DEPTH, + OUTPUT_REG => false ) port map( - clk_wr => ICAP_Clock, - rst_wr => reset_icap, - put => out_data_put, - din => out_data, - full => out_data_full, - - clk_rd => Clock, - rst_rd => Reset, - got => read_got, - valid => read_valid, - dout => read_data + Write_Clock => ICAP_Clock, + Write_Reset => reset_icap, + Write_Put => out_data_put, + Write_DataIn => out_data, + Write_Full => out_data_full, + Write_EmptyState => open, + + Read_Clock => Clock, + Read_Reset => Reset, + Read_Valid => Read_Valid, + Read_DataOut => Read_Data, + Read_Got => Read_Got, + Read_FillState => open ); FSM: entity work.reconfig_ICAP_FSM From 87162394d7bc516ad6f427b8b5da8a344cb3aaa6 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 12:11:46 +0200 Subject: [PATCH 08/18] Removed EMACS, vim/vi, Kate setting lines. --- .sigasi/project.sigasi | 2 +- docs/IPCores/fifo/fifo_cc_got.rst | 16 +-- docs/IPCores/fifo/fifo_cc_got_tempgot.rst | 22 ++-- docs/IPCores/fifo/fifo_cc_got_tempput.rst | 22 ++-- docs/IPCores/fifo/fifo_ic_got.rst | 18 +-- src/arith/arith_Counter_Gray.vhdl | 2 +- src/arith/xilinx/arith_Adder_Wide_Xilinx.vhdl | 1 - .../xilinx/arith_CarryChain_inc_Xilinx.vhdl | 1 - src/bus/axi4/axi4_DeMux.vhdl | 22 ++-- src/bus/axi4/axi4_Full.pkg.vhdl | 106 +++++++++--------- src/fifo/fifo_cc_got.vhdl | 16 +-- src/fifo/fifo_cc_got_tempgot.vhdl | 22 ++-- src/fifo/fifo_cc_got_tempput.vhdl | 22 ++-- src/fifo/fifo_ic_got.vhdl | 36 +++--- src/io/build.pro | 5 +- src/io/pmod/build.pro | 24 ++++ src/io/pmod/pmod_USBUART.vhdl | 12 +- src/io/uart/uart_FIFO.vhdl | 14 +-- .../axi4lite/Register/TC_RandomReadWrite.vhdl | 3 - tb/cache/cache_CPU_tb.vhdl | 4 - tb/cache/cache_Memory_tb.vhdl | 8 +- tb/common/config_tb.vhdl | 4 - tb/common/physical_tb.vhdl | 4 - tb/common/project_configuration_AC701.vhdl | 4 - tb/common/project_configuration_Arty.vhdl | 4 - tb/common/project_configuration_ArtyS7.vhdl | 4 - .../project_configuration_ECP5Versa.vhdl | 4 - tb/common/project_configuration_GENERIC.vhdl | 10 +- tb/common/project_configuration_KC705.vhdl | 4 - tb/common/project_configuration_Nexys4.vhdl | 4 - .../project_configuration_Nexys4DDR.vhdl | 4 - tb/common/project_configuration_VC707.vhdl | 4 - tb/common/project_configuration_VC709.vhdl | 4 - tb/common/project_configuration_ZC706.vhdl | 4 - tb/common/project_configuration_ZedBoard.vhdl | 4 - tb/common/strings_tb.vhdl | 4 - .../TbOutOfOrderBuffer_WriteRead.vhdl | 3 - ...truct_OutOfOrderBuffer_TestController.vhdl | 3 - .../OutOfOrderBuffer/tb_OutOfOrderBuffer.vhdl | 3 - tb/dstruct/dstruct_DoubleEndedQueue_tb.vhdl | 3 - tb/dstruct/dstruct_Stack_tb.vhdl | 3 - tb/fifo/fifo_cc_got_tb.vhdl | 20 ++-- tb/fifo/fifo_cc_got_tempput_tb.vhdl | 16 +-- tb/fifo/fifo_ic_assembly_tb.vhdl | 4 - tb/fifo/fifo_ic_got_tb.vhdl | 24 ++-- tb/io/ddrio/ddrio_InOut_tb.vhdl | 4 - tb/io/ddrio/ddrio_In_tb.vhdl | 4 - tb/io/ddrio/ddrio_Out_tb.vhdl | 4 - tb/io/io_Debounce_tb.vhdl | 4 - tb/io/uart/uart_RX_tb.vhdl | 4 - tb/mem/lut/lut_Sine_tb.vhdl | 4 - tb/mem/mem_model.vhdl | 4 - .../ocram_EnhancedSimpleDualPort_tb.vhdl | 4 - tb/mem/ocram/ocram_SimpleDualPort_tb.vhdl | 4 - tb/mem/ocram/ocram_SimpleDualPort_wf_tb.vhdl | 4 - tb/mem/ocram/ocram_TrueDualPort_tb.vhdl | 4 - tb/mem/ocram/ocram_TrueDualPort_wf_tb.vhdl | 4 - tb/misc/gearbox/gearbox_Down_cc_tb.vhdl | 4 - tb/misc/gearbox/gearbox_Down_dc_tb.vhdl | 4 - tb/misc/gearbox/gearbox_Up_cc_tb.vhdl | 4 - tb/misc/gearbox/gearbox_Up_dc_tb.vhdl | 4 - tb/misc/misc_bit_lz_tb.vhdl | 4 - tb/misc/stat/stat_Average_tb.vhdl | 4 - tb/misc/stat/stat_Histogram_tb.vhdl | 4 - tb/misc/stat/stat_Maximum_tb.vhdl | 4 - tb/misc/stat/stat_Minimum_tb.vhdl | 4 - tb/sort/sort_LeastRecentlyUsed_Cache_tb.vhdl | 4 - tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl | 4 - .../sortnet/sortnet_OddEvenMergeSort_tb.vhdl | 4 - tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl | 4 - .../sortnet/sortnet_Stream_Adapter2_tb.vhdl | 4 - .../sortnet/sortnet_Stream_Adapter_tb.vhdl | 4 - tb/sort/sortnet/sortnet_tb.pkg.vhdl | 4 - 73 files changed, 219 insertions(+), 416 deletions(-) create mode 100644 src/io/pmod/build.pro diff --git a/.sigasi/project.sigasi b/.sigasi/project.sigasi index ecbf27169..ec2691e97 100644 --- a/.sigasi/project.sigasi +++ b/.sigasi/project.sigasi @@ -27,7 +27,7 @@ "dependencies": [ { "Quartus": { - "version": "Quartus25.3", + "version": "Quartus26.1", "targets": [ "altera_mf" ] diff --git a/docs/IPCores/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst index ade671852..6af8c4258 100644 --- a/docs/IPCores/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -29,34 +29,34 @@ be used as data storage. The actual memory type depends on the device architecture. See implementation for details. ``*STATE_*_BITS`` defines the granularity of the fill state indicator -``*state_*``. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -``fstate_rd`` is associated with the read clock domain and outputs the -guaranteed number of words available in the FIFO. ``estate_wr`` is associated +``*State``. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. +``FillState`` is associated with the read clock domain and outputs the +guaranteed number of words available in the FIFO. ``EmptyState`` is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the ``full`` or ``valid`` outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state. -``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +``FillState`` and ``EmptyState`` are combinatorial outputs and include an address comparator (subtractor) in their path. .. rubric:: Examples: -* FSTATE_RD_BITS = 1: +* FILL_STATE_BITS = 1: +-----------+----------------------+ - | fstate_rd | filled (at least) | + | FillState | filled (at least) | +===========+======================+ | 0 | 0/2 full | +-----------+----------------------+ | 1 | 1/2 full (half full) | +-----------+----------------------+ -* FSTATE_RD_BITS = 2: +* FILL_STATE_BITS = 2: +-----------+----------------------+ - | fstate_rd | filled (at least) | + | FillState | filled (at least) | +===========+======================+ | 0 | 0/4 full | +-----------+----------------------+ diff --git a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst index ace1b02c8..3bb15daef 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -35,8 +35,8 @@ The FIFO state upon a simultaneous assertion of ``commit`` and ``rollback`` is *undefined*! ``*STATE_*_BITS`` defines the granularity of the fill state indicator -``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs -the guaranteed number of words available in the FIFO. ``estate_wr`` is +``*State``. ``FillState`` is associated with the read clock domain and outputs +the guaranteed number of words available in the FIFO. ``EmptyState`` is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the ``full`` or ``valid`` outputs as @@ -45,22 +45,22 @@ the true fill state. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +``FillState`` and ``EmptyState`` are combinatorial outputs and include an address comparator (subtractor) in their path. **Examples:** -* FSTATE_RD_BITS = 1: +* FILL_STATE_BITS = 1: - * fstate_rd == 0 => 0/2 full - * fstate_rd == 1 => 1/2 full (half full) + * FillState == 0 => 0/2 full + * FillState == 1 => 1/2 full (half full) -* FSTATE_RD_BITS = 2: +* FILL_STATE_BITS = 2: - * fstate_rd == 0 => 0/4 full - * fstate_rd == 1 => 1/4 full - * fstate_rd == 2 => 2/4 full - * fstate_rd == 3 => 3/4 full + * FillState == 0 => 0/4 full + * FillState == 1 => 1/4 full + * FillState == 2 => 2/4 full + * FillState == 3 => 3/4 full diff --git a/docs/IPCores/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst index 500c1a268..6e6d6682d 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -35,8 +35,8 @@ The FIFO state upon a simultaneous assertion of ``commit`` and ``rollback`` is *undefined*. ``*STATE_*_BITS`` defines the granularity of the fill state indicator -``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs -the guaranteed number of words available in the FIFO. ``estate_wr`` is +``*State``. ``FillState`` is associated with the read clock domain and outputs +the guaranteed number of words available in the FIFO. ``EmptyState`` is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the ``full`` or ``valid`` outputs as @@ -45,22 +45,22 @@ the true fill state. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +``FillState`` and ``EmptyState`` are combinatorial outputs and include an address comparator (subtractor) in their path. **Examples:** -* FSTATE_RD_BITS = 1: +* FILL_STATE_BITS = 1: - * fstate_rd == 0 => 0/2 full - * fstate_rd == 1 => 1/2 full (half full) + * FillState == 0 => 0/2 full + * FillState == 1 => 1/2 full (half full) -* FSTATE_RD_BITS = 2: +* FILL_STATE_BITS = 2: - * fstate_rd == 0 => 0/4 full - * fstate_rd == 1 => 1/4 full - * fstate_rd == 2 => 2/4 full - * fstate_rd == 3 => 3/4 full + * FillState == 0 => 0/4 full + * FillState == 1 => 1/4 full + * FillState == 2 => 2/4 full + * FillState == 3 => 3/4 full diff --git a/docs/IPCores/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst index 798d13d35..16d229e47 100644 --- a/docs/IPCores/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -34,8 +34,8 @@ used as data storage. The actual memory type depends on the device architecture. See implementation for details. ``*STATE_*_BITS`` defines the granularity of the fill state indicator -``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs -the guaranteed number of words available in the FIFO. ``estate_wr`` is +``*State``. ``FillState`` is associated with the read clock domain and outputs +the guaranteed number of words available in the FIFO. ``EmptyState`` is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the ``full`` or ``valid`` outputs as @@ -44,17 +44,17 @@ the true fill state. If a fill state is not of interest, set *STATE_*_BITS = 0. -``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +``FillState`` and ``EmptyState`` are combinatorial outputs and include an address comparator (subtractor) in their path. Examples: -- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full - fstate_rd == 1 => 1/2 full (half full) +- FILL_STATE_BITS = 1: FillState == 0 => 0/2 full + FillState == 1 => 1/2 full (half full) -- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full - fstate_rd == 1 => 1/4 full - fstate_rd == 2 => 2/4 full - fstate_rd == 3 => 3/4 full +- FILL_STATE_BITS = 2: FillState == 0 => 0/4 full + FillState == 1 => 1/4 full + FillState == 2 => 2/4 full + FillState == 3 => 3/4 full diff --git a/src/arith/arith_Counter_Gray.vhdl b/src/arith/arith_Counter_Gray.vhdl index a8c31c780..af8accd04 100644 --- a/src/arith/arith_Counter_Gray.vhdl +++ b/src/arith/arith_Counter_Gray.vhdl @@ -52,7 +52,7 @@ architecture rtl of arith_Counter_Gray is -- purpose: gray constant encoder function gray_encode (val : natural; len : positive) return unsigned is - variable bin : unsigned(len-1 downto 0) := to_unsigned(val, len); + constant bin : unsigned(len-1 downto 0) := to_unsigned(val, len); begin if len = 1 then return bin; diff --git a/src/arith/xilinx/arith_Adder_Wide_Xilinx.vhdl b/src/arith/xilinx/arith_Adder_Wide_Xilinx.vhdl index 99ea0ad7b..3d0dca2f0 100644 --- a/src/arith/xilinx/arith_Adder_Wide_Xilinx.vhdl +++ b/src/arith/xilinx/arith_Adder_Wide_Xilinx.vhdl @@ -461,7 +461,6 @@ begin genCCA: if ARCH = CCA generate constant M : positive := HI-LO+1; constant D : positive := M/2; - constant H : positive := (D+5)/6; signal pl : std_logic_vector(M-D-1 downto 0); signal pc : std_logic_vector(M-D downto 0); diff --git a/src/arith/xilinx/arith_CarryChain_inc_Xilinx.vhdl b/src/arith/xilinx/arith_CarryChain_inc_Xilinx.vhdl index 0fbdec3cf..f4b4364c0 100644 --- a/src/arith/xilinx/arith_CarryChain_inc_Xilinx.vhdl +++ b/src/arith/xilinx/arith_CarryChain_inc_Xilinx.vhdl @@ -50,7 +50,6 @@ end entity; architecture rtl of arith_CarryChain_inc_Xilinx is signal ci : std_logic_vector(BITS downto 0); - signal co : std_logic_vector(BITS downto 0); begin ci(0) <= CarryIn; diff --git a/src/bus/axi4/axi4_DeMux.vhdl b/src/bus/axi4/axi4_DeMux.vhdl index 03b446c29..b5a9da175 100644 --- a/src/bus/axi4/axi4_DeMux.vhdl +++ b/src/bus/axi4/axi4_DeMux.vhdl @@ -88,16 +88,16 @@ architecture rtl of axi4_DeMux is constant RESPONSE_FIFO_DEPTH : positive := 16; --Using SRL16E, depth is maximum 16 constant PORTS : positive := Out_M2S'length; - constant PORT_BITS : positive := log2ceilnz(PORTS); + -- constant PORT_BITS : positive := log2ceilnz(PORTS); constant IN_AW_ID_BITS : natural := In_M2S.AWID'length; constant Out_AW_ID_BITS : natural := Out_M2S(Out_M2S'low).AWID'length; - constant IN_AR_ID_BITS : natural := In_M2S.ARID'length; + -- constant IN_AR_ID_BITS : natural := In_M2S.ARID'length; constant Out_AR_ID_BITS : natural := Out_M2S(Out_M2S'low).ARID'length; constant ADDRESS_BITS : natural := imin(In_M2S.AWAddr'length, Out_M2S(0).AWAddr'length); constant DATA_BITS : natural := In_M2S.WData'length; - constant STRB_BITS : natural := In_M2S.WData'length / 8; + -- constant STRB_BITS : natural := In_M2S.WData'length / 8; constant CACHE_BITS : natural := In_M2S.AWCache'length; constant PROTECT_BITS : natural := In_M2S.AWProt'length; constant RESPONSE_BITS : natural := In_S2M.RResp'length; @@ -197,7 +197,7 @@ begin ); signal Address_hit : std_logic_vector(PORTS -1 downto 0); - constant MUX_DATA_BITS : natural := isum(BACKWARD_BIT_VEC); + -- constant MUX_DATA_BITS : natural := isum(BACKWARD_BIT_VEC); signal Mux_In_M2S : T_AXI4Stream_M2S_VECTOR(0 to PORTS)(Data(isum(BACKWARD_BIT_VEC) - 1 downto 0), Keep(0 downto 0), User(0 downto 0), ID(0 downto 0), Dest(0 downto 0)); signal Mux_In_S2M : T_AXI4Stream_S2M_VECTOR(0 to PORTS)(User(0 downto 0)); @@ -205,7 +205,7 @@ begin signal Mux_Out_S2M : T_AXI4Stream_S2M(User(0 downto 0)); signal Response_fifo_put : std_logic; - signal Response_fifo_ful : std_logic; + signal Response_fifo_ful : std_logic; -- FIXME: this signal is unused. signal Response_fifo_got : std_logic; signal Response_fifo_dout : std_logic_vector(ID_BITS-1 downto 0); signal Response_fifo_vld : std_logic; @@ -397,7 +397,7 @@ begin Response_fifo : entity work.fifo_Shift generic map( - DATA_BITS => ID_BITS, + DATA_BITS => ID_BITS, MIN_DEPTH => RESPONSE_FIFO_DEPTH ) port map( @@ -406,14 +406,14 @@ begin Reset => Reset, -- Writing Interface - Put => Response_fifo_put, - DataIn => In_M2S_write.ARID, - Full => Response_fifo_ful, + Put => Response_fifo_put, + DataIn => In_M2S_write.ARID, + Full => Response_fifo_ful, -- FIXME: this signal is unused -- Reading Interface - Got => Response_fifo_got, + Got => Response_fifo_got, DataOut => Response_fifo_dout, - Valid => Response_fifo_vld + Valid => Response_fifo_vld ); Mux_In_M2S(PORTS).Valid <= Response_fifo_vld; diff --git a/src/bus/axi4/axi4_Full.pkg.vhdl b/src/bus/axi4/axi4_Full.pkg.vhdl index db1a02bfb..a1564edcf 100644 --- a/src/bus/axi4/axi4_Full.pkg.vhdl +++ b/src/bus/axi4/axi4_Full.pkg.vhdl @@ -636,23 +636,23 @@ package body axi4_Full is function Initialize_AXI4_Bus_S2M(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_S2M is variable var : T_AXI4_Bus_S2M( - BID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), RID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), - BUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), RUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), - RData(DataBits - 1 downto 0) + BID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), RID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), + BUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), RUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), + RData(DataBits - 1 downto 0) ) := ( - AWReady => Value, - WReady => Value, - BValid => Value, - BResp => (others => Value), - BID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), - BUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), - ARReady => Value, - RValid => Value, - RData => (DataBits - 1 downto 0 => Value), - RResp => (others => Value), - RID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), - RLast => Value, - RUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value) + AWReady => Value, + WReady => Value, + BValid => Value, + BResp => (others => Value), + BID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), + BUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), + ARReady => Value, + RValid => Value, + RData => (DataBits - 1 downto 0 => Value), + RResp => (others => Value), + RID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), + RLast => Value, + RUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value) ); begin return var; @@ -660,42 +660,42 @@ package body axi4_Full is function Initialize_AXI4_Bus_M2S(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_M2S is variable var : T_AXI4_Bus_M2S( - AWID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), ARID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), - AWUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), ARUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), WUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), - WData(DataBits - 1 downto 0), WStrb((DataBits / 8) - 1 downto 0), - AWAddr(AddressBits - 1 downto 0), ARAddr(AddressBits - 1 downto 0) + AWID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), ARID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), + AWUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), ARUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), WUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), + WData(DataBits - 1 downto 0), WStrb((DataBits / 8) - 1 downto 0), + AWAddr(AddressBits - 1 downto 0), ARAddr(AddressBits - 1 downto 0) ) := ( - AWValid => Value, - AWCache => (others => Value), - AWAddr => (AddressBits - 1 downto 0 => Value), - AWProt => (others => Value), - AWID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), - AWLen => (others => Value), - AWSize => (others => Value), - AWBurst => (others => Value), - AWLock => (others => Value), - AWQOS => (others => Value), - AWRegion => (others => Value), - AWUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), - WValid => Value, - WData => (DataBits - 1 downto 0 => Value), - WStrb => ((DataBits / 8) - 1 downto 0 => Value), - WLast => Value, - WUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), - BReady => Value, - ARValid => Value, - ARCache => (others => Value), - ARAddr => (AddressBits - 1 downto 0 => Value), - ARProt => (others => Value), - ARID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), - ARLen => (others => Value), - ARSize => (others => Value), - ARBurst => (others => Value), - ARLock => (others => Value), - ARQOS => (others => Value), - ARRegion => (others => Value), - ARUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), - RReady => Value + AWValid => Value, + AWCache => (others => Value), + AWAddr => (AddressBits - 1 downto 0 => Value), + AWProt => (others => Value), + AWID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), + AWLen => (others => Value), + AWSize => (others => Value), + AWBurst => (others => Value), + AWLock => (others => Value), + AWQOS => (others => Value), + AWRegion => (others => Value), + AWUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), + WValid => Value, + WData => (DataBits - 1 downto 0 => Value), + WStrb => ((DataBits / 8) - 1 downto 0 => Value), + WLast => Value, + WUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), + BReady => Value, + ARValid => Value, + ARCache => (others => Value), + ARAddr => (AddressBits - 1 downto 0 => Value), + ARProt => (others => Value), + ARID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), + ARLen => (others => Value), + ARSize => (others => Value), + ARBurst => (others => Value), + ARLock => (others => Value), + ARQOS => (others => Value), + ARRegion => (others => Value), + ARUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), + RReady => Value ); begin return var; @@ -704,8 +704,8 @@ package body axi4_Full is function Initialize_AXI4_Bus(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0) return T_AXI4_Bus is begin return ( - M2S => Initialize_AXI4_Bus_M2S(AddressBits, DataBits, UserBits, IDBits), - S2M => Initialize_AXI4_Bus_S2M(AddressBits, DataBits, UserBits, IDBits) + M2S => Initialize_AXI4_Bus_M2S(AddressBits, DataBits, UserBits, IDBits), + S2M => Initialize_AXI4_Bus_S2M(AddressBits, DataBits, UserBits, IDBits) ); end function; diff --git a/src/fifo/fifo_cc_got.vhdl b/src/fifo/fifo_cc_got.vhdl index 7c3ffaef9..1edddb87c 100644 --- a/src/fifo/fifo_cc_got.vhdl +++ b/src/fifo/fifo_cc_got.vhdl @@ -20,33 +20,33 @@ -- -- ``*STATE_*_BITS`` defines the granularity of the fill state indicator -- ``*state_*``. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. --- ``fstate_rd`` is associated with the read clock domain and outputs the --- guaranteed number of words available in the FIFO. ``estate_wr`` is associated +-- ``FillState`` is associated with the read clock domain and outputs the +-- guaranteed number of words available in the FIFO. ``EmptyState`` is associated -- with the write clock domain and outputs the number of words that is -- guaranteed to be accepted by the FIFO without a capacity overflow. Note that -- both these indicators cannot replace the ``full`` or ``valid`` outputs as -- they may be implemented as giving pessimistic bounds that are minimally off -- the true fill state. -- --- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- ``FillState`` and ``EmptyState`` are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- .. rubric:: Examples: -- --- * FSTATE_RD_BITS = 1: +-- * FILL_STATE_BITS = 1: -- -- +-----------+----------------------+ --- | fstate_rd | filled (at least) | +-- | FillState | filled (at least) | -- +===========+======================+ -- | 0 | 0/2 full | -- +-----------+----------------------+ -- | 1 | 1/2 full (half full) | -- +-----------+----------------------+ -- --- * FSTATE_RD_BITS = 2: +-- * FILL_STATE_BITS = 2: -- -- +-----------+----------------------+ --- | fstate_rd | filled (at least) | +-- | FillState | filled (at least) | -- +===========+======================+ -- | 0 | 0/4 full | -- +-----------+----------------------+ @@ -180,7 +180,7 @@ begin FillState <= (others => '0'); else generate - assert LUT_SHIFT_LOGIC = false report "PoC.fifo_cc_got.vhdl :: Implementing FIFO in LUT_SHIFT_LOGIC was not possible. Following conditions are not met: 'MIN_DEPTH <= 32 and D_BITS <= 128 and ESTATE_WR_BITS = 0 and FSTATE_RD_BITS = 0'" + assert LUT_SHIFT_LOGIC = false report "PoC.fifo_cc_got.vhdl :: Implementing FIFO in LUT_SHIFT_LOGIC was not possible. Following conditions are not met: 'MIN_DEPTH <= 32 and D_BITS <= 128 and EMPTY_STATE_BITS = 0 and FILL_STATE_BITS = 0'" severity warning; ----------------------------------------------------------------------------- -- Pointer Logic diff --git a/src/fifo/fifo_cc_got_tempgot.vhdl b/src/fifo/fifo_cc_got_tempgot.vhdl index 0275873a2..ad47e9762 100644 --- a/src/fifo/fifo_cc_got_tempgot.vhdl +++ b/src/fifo/fifo_cc_got_tempgot.vhdl @@ -25,8 +25,8 @@ -- *undefined*! -- -- ``*STATE_*_BITS`` defines the granularity of the fill state indicator --- ``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. ``estate_wr`` is +-- ``*State``. ``FillState`` is associated with the read clock domain and outputs +-- the guaranteed number of words available in the FIFO. ``EmptyState`` is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the ``full`` or ``valid`` outputs as @@ -35,22 +35,22 @@ -- -- If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -- --- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- ``FillState`` and ``EmptyState`` are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- **Examples:** -- --- * FSTATE_RD_BITS = 1: +-- * FILL_STATE_BITS = 1: -- --- * fstate_rd == 0 => 0/2 full --- * fstate_rd == 1 => 1/2 full (half full) +-- * FillState == 0 => 0/2 full +-- * FillState == 1 => 1/2 full (half full) -- --- * FSTATE_RD_BITS = 2: +-- * FILL_STATE_BITS = 2: -- --- * fstate_rd == 0 => 0/4 full --- * fstate_rd == 1 => 1/4 full --- * fstate_rd == 2 => 2/4 full --- * fstate_rd == 3 => 3/4 full +-- * FillState == 0 => 0/4 full +-- * FillState == 1 => 1/4 full +-- * FillState == 2 => 2/4 full +-- * FillState == 3 => 3/4 full -- -- License: -- ============================================================================= diff --git a/src/fifo/fifo_cc_got_tempput.vhdl b/src/fifo/fifo_cc_got_tempput.vhdl index 532c92a8e..0eb4cbaa0 100644 --- a/src/fifo/fifo_cc_got_tempput.vhdl +++ b/src/fifo/fifo_cc_got_tempput.vhdl @@ -25,8 +25,8 @@ -- *undefined*. -- -- ``*STATE_*_BITS`` defines the granularity of the fill state indicator --- ``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. ``estate_wr`` is +-- ``*state_*``. ``FillState`` is associated with the read clock domain and outputs +-- the guaranteed number of words available in the FIFO. ``EmptyState`` is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the ``full`` or ``valid`` outputs as @@ -35,22 +35,22 @@ -- -- If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -- --- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- ``FillState`` and ``EmptyState`` are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- **Examples:** -- --- * FSTATE_RD_BITS = 1: +-- * FILL_STATE_BITS = 1: -- --- * fstate_rd == 0 => 0/2 full --- * fstate_rd == 1 => 1/2 full (half full) +-- * FillState == 0 => 0/2 full +-- * FillState == 1 => 1/2 full (half full) -- --- * FSTATE_RD_BITS = 2: +-- * FILL_STATE_BITS = 2: -- --- * fstate_rd == 0 => 0/4 full --- * fstate_rd == 1 => 1/4 full --- * fstate_rd == 2 => 2/4 full --- * fstate_rd == 3 => 3/4 full +-- * FillState == 0 => 0/4 full +-- * FillState == 1 => 1/4 full +-- * FillState == 2 => 2/4 full +-- * FillState == 3 => 3/4 full -- -- License: -- ============================================================================= diff --git a/src/fifo/fifo_ic_got.vhdl b/src/fifo/fifo_ic_got.vhdl index 88d80d987..aa6eae6ec 100644 --- a/src/fifo/fifo_ic_got.vhdl +++ b/src/fifo/fifo_ic_got.vhdl @@ -23,8 +23,8 @@ -- architecture. See implementation for details. -- -- ``*STATE_*_BITS`` defines the granularity of the fill state indicator --- ``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. ``estate_wr`` is +-- ``*state_*``. ``FillState`` is associated with the read clock domain and outputs +-- the guaranteed number of words available in the FIFO. ``EmptyState`` is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the ``full`` or ``valid`` outputs as @@ -33,17 +33,17 @@ -- -- If a fill state is not of interest, set *STATE_*_BITS = 0. -- --- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- ``FillState`` and ``EmptyState`` are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- - FILL_STATE_BITS = 1: FillState == 0 => 0/2 full +-- FillState == 1 => 1/2 full (half full) -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- - FILL_STATE_BITS = 2: FillState == 0 => 0/4 full +-- FillState == 1 => 1/4 full +-- FillState == 2 => 2/4 full +-- FillState == 3 => 3/4 full -- -- License: -- ============================================================================= @@ -305,28 +305,26 @@ begin -- Fill State ----------------------------------------------------------------------------- -- Write Clock Domain - gEstateWr: if EMPTY_STATE_BITS >= 1 generate + gEmptyState: if EMPTY_STATE_BITS = 0 generate + Write_EmptyState <= "X"; + else generate signal d : unsigned(ADDRESS_BITS-1 downto 0); begin d <= gray2bin(OPc(ADDRESS_BITS-1 downto 0)) + not gray2bin(IP0(ADDRESS_BITS-1 downto 0)); Write_EmptyState <= (others => '0') when Ful = '1' else std_logic_vector(d(d'left downto d'left-EMPTY_STATE_BITS+1)); - end generate gEstateWr; - gNoEstateWr: if EMPTY_STATE_BITS = 0 generate - Write_EmptyState <= "X"; - end generate gNoEstateWr; + end generate; -- Read Clock Domain - gFstateRd: if FILL_STATE_BITS >= 1 generate + gFillState: if FILL_STATE_BITS = 0 generate + Read_FillState <= "X"; + else generate signal d : unsigned(ADDRESS_BITS-1 downto 0); begin d <= gray2bin(IPc(ADDRESS_BITS-1 downto 0)) + not gray2bin(OP0(ADDRESS_BITS-1 downto 0)); Read_FillState <= (others => '0') when Avl = '0' else std_logic_vector(d(d'left downto d'left-FILL_STATE_BITS+1)); - end generate gFstateRd; - gNoFstateRd: if FILL_STATE_BITS = 0 generate - Read_FillState <= "X"; - end generate gNoFstateRd; + end generate; ----------------------------------------------------------------------------- -- Memory Instantiation diff --git a/src/io/build.pro b/src/io/build.pro index 9d4b8a62c..1da11304f 100644 --- a/src/io/build.pro +++ b/src/io/build.pro @@ -37,9 +37,6 @@ include ./uart disabled ./iic/iic.pro disabled ./fan/fan.pro -analyze ./pmod/pmod.pkg.vhdl -analyze ./pmod/pmod_KYPD.vhdl -analyze ./pmod/pmod_SSD.vhdl -disabled ./pmod/pmod_USBUART.vhdl +include ./pmod disabled ./jtag/jtag.pkg.vhdl disabled ./led/led.pkg.vhdl diff --git a/src/io/pmod/build.pro b/src/io/pmod/build.pro new file mode 100644 index 000000000..070e5278d --- /dev/null +++ b/src/io/pmod/build.pro @@ -0,0 +1,24 @@ +# ============================================================================= +# Authors: Patrick Lehmann +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./pmod.pkg.vhdl +analyze ./pmod_KYPD.vhdl +analyze ./pmod_SSD.vhdl +analyze ./pmod_USBUART.vhdl diff --git a/src/io/pmod/pmod_USBUART.vhdl b/src/io/pmod/pmod_USBUART.vhdl index 5b3693393..f7543f2b2 100644 --- a/src/io/pmod/pmod_USBUART.vhdl +++ b/src/io/pmod/pmod_USBUART.vhdl @@ -45,13 +45,13 @@ entity pmod_USBUART is Clock : in std_logic; Reset : in std_logic; - TX_put : in std_logic; + TX_Put : in std_logic; TX_Data : in std_logic_vector(7 downto 0); TX_Full : out std_logic; RX_Valid : out std_logic; RX_Data : out std_logic_vector(7 downto 0); - RX_got : in std_logic; + RX_Got : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; @@ -71,9 +71,9 @@ begin ADD_INPUT_SYNCHRONIZERS => TRUE, TX_MIN_DEPTH => 32, - TX_ESTATE_BITS => 0, + TX_EMPTY_STATE_BITS => 0, RX_MIN_DEPTH => 32, - RX_FSTATE_BITS => 0, + RX_FILL_STATE_BITS => 0, FLOWCONTROL => UART_FLOWCONTROL_RTS_CTS ) @@ -82,14 +82,14 @@ begin Reset => Reset, TXFIFO_Reset => Reset, - TX_put => TX_put, + TX_put => TX_Put, TX_Data => TX_Data, TX_Full => TX_Full, RXFIFO_Reset => Reset, RX_Valid => RX_Valid, RX_Data => RX_Data, - RX_got => RX_got, + RX_got => RX_Got, UART_TX => UART_TX, UART_RX => UART_RX, diff --git a/src/io/uart/uart_FIFO.vhdl b/src/io/uart/uart_FIFO.vhdl index c2b3ce503..841af3c83 100644 --- a/src/io/uart/uart_FIFO.vhdl +++ b/src/io/uart/uart_FIFO.vhdl @@ -15,7 +15,7 @@ -- := For exmaple: -- FLOWCTRL_XOFF_THRESHOLD is set to 0.75, if fifo filled upto = FIFO_DEPTH*0.75 -- gives the backpressure based the flow control that being used. To know more about --- TX_ESTATE_BITS,RX_FSTATE_BITS please refer 'fifo_cc_got' module. User can change the +-- TX_EMPTY_STATE_BITS, RX_FILL_STATE_BITS please refer 'fifo_cc_got' module. User can change the -- SWFC_XON/XOFF_CHAR if needed. -- -- License: @@ -61,9 +61,9 @@ entity uart_FIFO is -- Buffer Dimensioning TX_MIN_DEPTH : positive := 16; - TX_EMPTY_STATE_BITS : natural := 0; -- XXX: adjust to FIFO naming + TX_EMPTY_STATE_BITS : natural := 0; -- XXX: adjust to FIFO naming RX_MIN_DEPTH : positive := 16; - RX_FILL_STATE_BITS : natural := 0; + RX_FILL_STATE_BITS : natural := 0; FLOWCTRL_XON_THRESHOLD : real := 0.0625; FLOWCTRL_XOFF_THRESHOLD : real := 0.75; @@ -274,8 +274,8 @@ begin -- Hardware Flow Control -- =========================================================================== genHWFC1 : if FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS generate - constant RX_FSTATE_UPPER_LIMIT : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FILL_STATE_BITS)); - constant RX_FSTATE_LOWER_LIMIT : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FILL_STATE_BITS)); + constant RX_FILL_STATE_UPPER_LIMIT : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FILL_STATE_BITS)); + constant RX_FILL_STATE_LOWER_LIMIT : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FILL_STATE_BITS)); begin --assert false report"FLOWCONTROL=" & T_IO_UART_FLOWCONTROL_KIND'image(FLOWCONTROL) & " is currently not supported!" severity failure; @@ -293,9 +293,9 @@ begin if TXUART_Full = '0' then if Reset = '1' then UART_RTS<='1'; - elsif (to_integer(unsigned(RX_FillState_int)) >= RX_FSTATE_UPPER_LIMIT) then + elsif (to_integer(unsigned(RX_FillState_int)) >= RX_FILL_STATE_UPPER_LIMIT) then UART_RTS<='0'; - elsif (to_integer(unsigned(RX_FillState_int)) <= RX_FSTATE_LOWER_LIMIT) then + elsif (to_integer(unsigned(RX_FillState_int)) <= RX_FILL_STATE_LOWER_LIMIT) then UART_RTS<='1'; end if; end if; diff --git a/tb/bus/axi4lite/Register/TC_RandomReadWrite.vhdl b/tb/bus/axi4lite/Register/TC_RandomReadWrite.vhdl index c2e1f4710..a9c846312 100644 --- a/tb/bus/axi4lite/Register/TC_RandomReadWrite.vhdl +++ b/tb/bus/axi4lite/Register/TC_RandomReadWrite.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: -- Iqbal Asif (PLC2 Design GmbH) diff --git a/tb/cache/cache_CPU_tb.vhdl b/tb/cache/cache_CPU_tb.vhdl index 099c5ea40..c5e467d03 100644 --- a/tb/cache/cache_CPU_tb.vhdl +++ b/tb/cache/cache_CPU_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Martin Zabel -- diff --git a/tb/cache/cache_Memory_tb.vhdl b/tb/cache/cache_Memory_tb.vhdl index 48db0f822..a13bb8612 100644 --- a/tb/cache/cache_Memory_tb.vhdl +++ b/tb/cache/cache_Memory_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Martin Zabel -- @@ -223,11 +219,11 @@ begin put => mem2_rstb, din => mem2_rdata, full => open, -- should not overflow - estate_wr => open, + EmptyState => open, got => cache_rstb, dout => rply2_rdata, valid => rply2_valid, - fstate_rd => open); + FillState => open); -- The Write-Data Generator of the CPU wdata_prng: entity poc.arith_PRNG diff --git a/tb/common/config_tb.vhdl b/tb/common/config_tb.vhdl index 9f222d1d5..6435ed2cd 100644 --- a/tb/common/config_tb.vhdl +++ b/tb/common/config_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann diff --git a/tb/common/physical_tb.vhdl b/tb/common/physical_tb.vhdl index 33dd8f92c..f4f6fc66d 100644 --- a/tb/common/physical_tb.vhdl +++ b/tb/common/physical_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Testbench: Testing the physical package. -- diff --git a/tb/common/project_configuration_AC701.vhdl b/tb/common/project_configuration_AC701.vhdl index 86b5e2c44..f5c502449 100644 --- a/tb/common/project_configuration_AC701.vhdl +++ b/tb/common/project_configuration_AC701.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_Arty.vhdl b/tb/common/project_configuration_Arty.vhdl index 40ec32243..a8191cc82 100644 --- a/tb/common/project_configuration_Arty.vhdl +++ b/tb/common/project_configuration_Arty.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_ArtyS7.vhdl b/tb/common/project_configuration_ArtyS7.vhdl index edee602e5..52e093f03 100644 --- a/tb/common/project_configuration_ArtyS7.vhdl +++ b/tb/common/project_configuration_ArtyS7.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_ECP5Versa.vhdl b/tb/common/project_configuration_ECP5Versa.vhdl index cbf4a3f0d..2bfee0b06 100644 --- a/tb/common/project_configuration_ECP5Versa.vhdl +++ b/tb/common/project_configuration_ECP5Versa.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_GENERIC.vhdl b/tb/common/project_configuration_GENERIC.vhdl index a3fc84150..1d23f9ca5 100644 --- a/tb/common/project_configuration_GENERIC.vhdl +++ b/tb/common/project_configuration_GENERIC.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -33,9 +29,9 @@ package project_configuration is -- Change these lines to setup configuration. - constant MY_BOARD : string := "GENERIC"; -- a generic board - constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + constant MY_BOARD : string := "GENERIC"; -- a generic board + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- For internal use only - constant MY_VERBOSE : boolean := FALSE; + constant MY_VERBOSE : boolean := FALSE; end package; diff --git a/tb/common/project_configuration_KC705.vhdl b/tb/common/project_configuration_KC705.vhdl index ae97bfe3e..a55d60f65 100644 --- a/tb/common/project_configuration_KC705.vhdl +++ b/tb/common/project_configuration_KC705.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_Nexys4.vhdl b/tb/common/project_configuration_Nexys4.vhdl index 140ece777..7804f3a14 100644 --- a/tb/common/project_configuration_Nexys4.vhdl +++ b/tb/common/project_configuration_Nexys4.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/common/project_configuration_Nexys4DDR.vhdl b/tb/common/project_configuration_Nexys4DDR.vhdl index 7ca66a79b..ef5b95989 100644 --- a/tb/common/project_configuration_Nexys4DDR.vhdl +++ b/tb/common/project_configuration_Nexys4DDR.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/common/project_configuration_VC707.vhdl b/tb/common/project_configuration_VC707.vhdl index 0aa72b866..8f30ee1fa 100644 --- a/tb/common/project_configuration_VC707.vhdl +++ b/tb/common/project_configuration_VC707.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_VC709.vhdl b/tb/common/project_configuration_VC709.vhdl index 450b337c5..ba1fded8f 100644 --- a/tb/common/project_configuration_VC709.vhdl +++ b/tb/common/project_configuration_VC709.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_ZC706.vhdl b/tb/common/project_configuration_ZC706.vhdl index c285a3c25..f4ae27f75 100644 --- a/tb/common/project_configuration_ZC706.vhdl +++ b/tb/common/project_configuration_ZC706.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/project_configuration_ZedBoard.vhdl b/tb/common/project_configuration_ZedBoard.vhdl index 3f6be2a54..146dc5268 100644 --- a/tb/common/project_configuration_ZedBoard.vhdl +++ b/tb/common/project_configuration_ZedBoard.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/tb/common/strings_tb.vhdl b/tb/common/strings_tb.vhdl index ba24453b2..8faa19141 100644 --- a/tb/common/strings_tb.vhdl +++ b/tb/common/strings_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/dstruct/OutOfOrderBuffer/TbOutOfOrderBuffer_WriteRead.vhdl b/tb/dstruct/OutOfOrderBuffer/TbOutOfOrderBuffer_WriteRead.vhdl index 40e4354cd..d498b6b0c 100644 --- a/tb/dstruct/OutOfOrderBuffer/TbOutOfOrderBuffer_WriteRead.vhdl +++ b/tb/dstruct/OutOfOrderBuffer/TbOutOfOrderBuffer_WriteRead.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Iqbal Asif -- diff --git a/tb/dstruct/OutOfOrderBuffer/dstruct_OutOfOrderBuffer_TestController.vhdl b/tb/dstruct/OutOfOrderBuffer/dstruct_OutOfOrderBuffer_TestController.vhdl index 79ec21988..a0a6c135d 100644 --- a/tb/dstruct/OutOfOrderBuffer/dstruct_OutOfOrderBuffer_TestController.vhdl +++ b/tb/dstruct/OutOfOrderBuffer/dstruct_OutOfOrderBuffer_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Iqbal Asif -- diff --git a/tb/dstruct/OutOfOrderBuffer/tb_OutOfOrderBuffer.vhdl b/tb/dstruct/OutOfOrderBuffer/tb_OutOfOrderBuffer.vhdl index e14087de0..c431306ad 100644 --- a/tb/dstruct/OutOfOrderBuffer/tb_OutOfOrderBuffer.vhdl +++ b/tb/dstruct/OutOfOrderBuffer/tb_OutOfOrderBuffer.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Iqbal Asif -- diff --git a/tb/dstruct/dstruct_DoubleEndedQueue_tb.vhdl b/tb/dstruct/dstruct_DoubleEndedQueue_tb.vhdl index df03c0ca1..882fc16e2 100644 --- a/tb/dstruct/dstruct_DoubleEndedQueue_tb.vhdl +++ b/tb/dstruct/dstruct_DoubleEndedQueue_tb.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================ -- Authors: Jens Voss -- diff --git a/tb/dstruct/dstruct_Stack_tb.vhdl b/tb/dstruct/dstruct_Stack_tb.vhdl index a8102ac46..1a69b7089 100644 --- a/tb/dstruct/dstruct_Stack_tb.vhdl +++ b/tb/dstruct/dstruct_Stack_tb.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================ -- Authors: Jens Voss -- diff --git a/tb/fifo/fifo_cc_got_tb.vhdl b/tb/fifo/fifo_cc_got_tb.vhdl index e99426b0a..20889397c 100644 --- a/tb/fifo/fifo_cc_got_tb.vhdl +++ b/tb/fifo/fifo_cc_got_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Thomas B. Preusser -- @@ -53,8 +49,8 @@ architecture tb of fifo_cc_got_tb is -- component generics constant D_BITS : positive := 8; constant MIN_DEPTH : positive := 30; - constant ESTATE_WR_BITS : natural := 2; - constant FSTATE_RD_BITS : natural := 2; + constant EMPTY_STATE_BITS : natural := 2; + constant FILL_STATE_BITS : natural := 2; -- Clock Control signal rst : std_logic; @@ -78,11 +74,11 @@ begin signal put : std_logic; signal din : std_logic_vector(D_BITS-1 downto 0); signal full : std_logic; - signal estate_wr : std_logic_vector(ESTATE_WR_BITS - 1 downto 0); + signal EmptyState : std_logic_vector(EMPTY_STATE_BITS - 1 downto 0); signal got : std_logic; signal dout : std_logic_vector(D_BITS-1 downto 0); signal valid : std_logic; - signal fstate_rd : std_logic_vector(FSTATE_RD_BITS - 1 downto 0); + signal FillState : std_logic_vector(FILL_STATE_BITS - 1 downto 0); begin @@ -93,8 +89,8 @@ begin STATE_REG => STATE_REG, DATA_REG => DATA_REG, OUTPUT_REG => OUTPUT_REG, - ESTATE_WR_BITS => ESTATE_WR_BITS, - FSTATE_RD_BITS => FSTATE_RD_BITS + EMPTY_STATE_BITS => EMPTY_STATE_BITS, + FILL_STATE_BITS => FILL_STATE_BITS ) port map ( rst => rst, @@ -102,11 +98,11 @@ begin put => put, din => din, full => full, - estate_wr => estate_wr, + EmptyState => EmptyState, got => got, dout => dout, valid => valid, - fstate_rd => fstate_rd + FillState => FillState ); -- Writer diff --git a/tb/fifo/fifo_cc_got_tempput_tb.vhdl b/tb/fifo/fifo_cc_got_tempput_tb.vhdl index 1417908db..242a86009 100644 --- a/tb/fifo/fifo_cc_got_tempput_tb.vhdl +++ b/tb/fifo/fifo_cc_got_tempput_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Thomas B. Preusser -- @@ -52,8 +48,8 @@ architecture tb of fifo_cc_got_tempput_tb is -- component generics constant D_BITS : positive := 8; constant MIN_DEPTH : positive := 8; - constant ESTATE_WR_BITS : natural := 2; - constant FSTATE_RD_BITS : natural := 2; + constant EMPTY_STATE_BITS : natural := 2; + constant FILL_STATE_BITS : natural := 2; constant ISPEC : string := "C C Cccccpppp pppp c ccc pp Cppppp ppp rp RpC"; constant OSPEC : string := "ggg gggggggg ggg G G"; @@ -165,8 +161,8 @@ begin DATA_REG => DATA_REG, STATE_REG => STATE_REG, OUTPUT_REG => OUTPUT_REG, - ESTATE_WR_BITS => ESTATE_WR_BITS, - FSTATE_RD_BITS => FSTATE_RD_BITS + EMPTY_STATE_BITS => EMPTY_STATE_BITS, + FILL_STATE_BITS => FILL_STATE_BITS ) port map ( rst => rst, @@ -175,14 +171,14 @@ begin put => put, din => di, full => ful, - estate_wr => open, + EmptyState => open, commit => commit, rollback => rollback, got => got, dout => do, valid => vld, - fstate_rd => open + FillState => open ); -- Reader diff --git a/tb/fifo/fifo_ic_assembly_tb.vhdl b/tb/fifo/fifo_ic_assembly_tb.vhdl index 4d1de5c75..5b5ff8b02 100644 --- a/tb/fifo/fifo_ic_assembly_tb.vhdl +++ b/tb/fifo/fifo_ic_assembly_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/tb/fifo/fifo_ic_got_tb.vhdl b/tb/fifo/fifo_ic_got_tb.vhdl index e09f359d4..184389055 100644 --- a/tb/fifo/fifo_ic_got_tb.vhdl +++ b/tb/fifo/fifo_ic_got_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- @@ -52,8 +48,8 @@ architecture tb of fifo_ic_got_tb is constant D_BITS : positive := 9; constant MIN_DEPTH : positive := 8; constant OUTPUT_REG : boolean := true; - constant ESTATE_WR_BITS : natural := 2; - constant FSTATE_RD_BITS : natural := 2; + constant EMPTY_STATE_BITS : natural := 2; + constant FILL_STATE_BITS : natural := 2; -- Sequence Generator constant GEN : bit_vector := "100110001"; @@ -155,8 +151,8 @@ begin D_BITS => D_BITS, MIN_DEPTH => MIN_DEPTH, OUTPUT_REG => OUTPUT_REG, - ESTATE_WR_BITS => ESTATE_WR_BITS, - FSTATE_RD_BITS => FSTATE_RD_BITS + EMPTY_STATE_BITS => EMPTY_STATE_BITS, + FILL_STATE_BITS => FILL_STATE_BITS ) port map ( clk_wr => clk0, @@ -164,14 +160,14 @@ begin put => put0, din => di0, full => ful0, - estate_wr => open, + EmptyState => open, clk_rd => clk1, rst_rd => rst, got => got1, valid => vld1, dout => do1, - fstate_rd => open + FillState => open ); ----------------------------------------------------------------------------- @@ -216,8 +212,8 @@ begin DATA_REG => true, D_BITS => D_BITS, MIN_DEPTH => MIN_DEPTH, - ESTATE_WR_BITS => ESTATE_WR_BITS, - FSTATE_RD_BITS => FSTATE_RD_BITS + EMPTY_STATE_BITS => EMPTY_STATE_BITS, + FILL_STATE_BITS => FILL_STATE_BITS ) port map ( clk_wr => clk1, @@ -225,14 +221,14 @@ begin put => put1, din => di1, full => ful1, - estate_wr => open, + EmptyState => open, clk_rd => clk2, rst_rd => rst, got => got2, valid => vld2, dout => do2, - fstate_rd => open + FillState => open ); ----------------------------------------------------------------------------- diff --git a/tb/io/ddrio/ddrio_InOut_tb.vhdl b/tb/io/ddrio/ddrio_InOut_tb.vhdl index 38aaf4d3a..b1b1e3176 100644 --- a/tb/io/ddrio/ddrio_InOut_tb.vhdl +++ b/tb/io/ddrio/ddrio_InOut_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Martin Zabel -- diff --git a/tb/io/ddrio/ddrio_In_tb.vhdl b/tb/io/ddrio/ddrio_In_tb.vhdl index f80862c25..819e7667c 100644 --- a/tb/io/ddrio/ddrio_In_tb.vhdl +++ b/tb/io/ddrio/ddrio_In_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Martin Zabel -- diff --git a/tb/io/ddrio/ddrio_Out_tb.vhdl b/tb/io/ddrio/ddrio_Out_tb.vhdl index 7ba99de8d..dbed97ff7 100644 --- a/tb/io/ddrio/ddrio_Out_tb.vhdl +++ b/tb/io/ddrio/ddrio_Out_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Martin Zabel -- diff --git a/tb/io/io_Debounce_tb.vhdl b/tb/io/io_Debounce_tb.vhdl index d37aaf18c..ce17ec5ab 100644 --- a/tb/io/io_Debounce_tb.vhdl +++ b/tb/io/io_Debounce_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/io/uart/uart_RX_tb.vhdl b/tb/io/uart/uart_RX_tb.vhdl index 944133881..3a32c340a 100644 --- a/tb/io/uart/uart_RX_tb.vhdl +++ b/tb/io/uart/uart_RX_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Patrick Lehmann -- diff --git a/tb/mem/lut/lut_Sine_tb.vhdl b/tb/mem/lut/lut_Sine_tb.vhdl index 4f3f6837b..12fd4cade 100644 --- a/tb/mem/lut/lut_Sine_tb.vhdl +++ b/tb/mem/lut/lut_Sine_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/mem/mem_model.vhdl b/tb/mem/mem_model.vhdl index e4588451f..3fa87e150 100644 --- a/tb/mem/mem_model.vhdl +++ b/tb/mem/mem_model.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Martin Zabel -- diff --git a/tb/mem/ocram/ocram_EnhancedSimpleDualPort_tb.vhdl b/tb/mem/ocram/ocram_EnhancedSimpleDualPort_tb.vhdl index 0fc79ce49..d29e1cac3 100644 --- a/tb/mem/ocram/ocram_EnhancedSimpleDualPort_tb.vhdl +++ b/tb/mem/ocram/ocram_EnhancedSimpleDualPort_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/tb/mem/ocram/ocram_SimpleDualPort_tb.vhdl b/tb/mem/ocram/ocram_SimpleDualPort_tb.vhdl index 6aa11c6fa..e3377a266 100644 --- a/tb/mem/ocram/ocram_SimpleDualPort_tb.vhdl +++ b/tb/mem/ocram/ocram_SimpleDualPort_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/tb/mem/ocram/ocram_SimpleDualPort_wf_tb.vhdl b/tb/mem/ocram/ocram_SimpleDualPort_wf_tb.vhdl index e7ca4535e..663cf4e89 100644 --- a/tb/mem/ocram/ocram_SimpleDualPort_wf_tb.vhdl +++ b/tb/mem/ocram/ocram_SimpleDualPort_wf_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/tb/mem/ocram/ocram_TrueDualPort_tb.vhdl b/tb/mem/ocram/ocram_TrueDualPort_tb.vhdl index af64cc23d..629124076 100644 --- a/tb/mem/ocram/ocram_TrueDualPort_tb.vhdl +++ b/tb/mem/ocram/ocram_TrueDualPort_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/tb/mem/ocram/ocram_TrueDualPort_wf_tb.vhdl b/tb/mem/ocram/ocram_TrueDualPort_wf_tb.vhdl index 8ab908f35..e388f8ccd 100644 --- a/tb/mem/ocram/ocram_TrueDualPort_wf_tb.vhdl +++ b/tb/mem/ocram/ocram_TrueDualPort_wf_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/tb/misc/gearbox/gearbox_Down_cc_tb.vhdl b/tb/misc/gearbox/gearbox_Down_cc_tb.vhdl index 3bff0b72a..621b2dafd 100644 --- a/tb/misc/gearbox/gearbox_Down_cc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_Down_cc_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/gearbox/gearbox_Down_dc_tb.vhdl b/tb/misc/gearbox/gearbox_Down_dc_tb.vhdl index 7d80ba017..1f7eb5357 100644 --- a/tb/misc/gearbox/gearbox_Down_dc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_Down_dc_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/gearbox/gearbox_Up_cc_tb.vhdl b/tb/misc/gearbox/gearbox_Up_cc_tb.vhdl index 86ec727ec..2b48b7d50 100644 --- a/tb/misc/gearbox/gearbox_Up_cc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_Up_cc_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/gearbox/gearbox_Up_dc_tb.vhdl b/tb/misc/gearbox/gearbox_Up_dc_tb.vhdl index d717669d9..dcafac698 100644 --- a/tb/misc/gearbox/gearbox_Up_dc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_Up_dc_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/misc_bit_lz_tb.vhdl b/tb/misc/misc_bit_lz_tb.vhdl index 3cf281730..31f0d0152 100644 --- a/tb/misc/misc_bit_lz_tb.vhdl +++ b/tb/misc/misc_bit_lz_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- =========================================================================== -- Testbench: Basic testbench for LZ-based bitstream compressor misc_bit_lz. -- diff --git a/tb/misc/stat/stat_Average_tb.vhdl b/tb/misc/stat/stat_Average_tb.vhdl index d4a7d54fd..442cc1d62 100644 --- a/tb/misc/stat/stat_Average_tb.vhdl +++ b/tb/misc/stat/stat_Average_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/stat/stat_Histogram_tb.vhdl b/tb/misc/stat/stat_Histogram_tb.vhdl index 9cd16adf8..97c4c77fa 100644 --- a/tb/misc/stat/stat_Histogram_tb.vhdl +++ b/tb/misc/stat/stat_Histogram_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/stat/stat_Maximum_tb.vhdl b/tb/misc/stat/stat_Maximum_tb.vhdl index d41cac9d4..5f130a574 100644 --- a/tb/misc/stat/stat_Maximum_tb.vhdl +++ b/tb/misc/stat/stat_Maximum_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/misc/stat/stat_Minimum_tb.vhdl b/tb/misc/stat/stat_Minimum_tb.vhdl index 510783a6d..3ec933d35 100644 --- a/tb/misc/stat/stat_Minimum_tb.vhdl +++ b/tb/misc/stat/stat_Minimum_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sort/sort_LeastRecentlyUsed_Cache_tb.vhdl b/tb/sort/sort_LeastRecentlyUsed_Cache_tb.vhdl index fe1a6da8b..14deeed8f 100644 --- a/tb/sort/sort_LeastRecentlyUsed_Cache_tb.vhdl +++ b/tb/sort/sort_LeastRecentlyUsed_Cache_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================ -- Authors: Patrick Lehmann -- Martin Zabel diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl index 8182bae50..2cdc7a777 100644 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl index cf00d06a2..ace8ac4f4 100644 --- a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl index 8af85e67a..875923e76 100644 --- a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl index 70e814a48..b8c3fb21f 100644 --- a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl +++ b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl index 1864b5d57..cbae59f0d 100644 --- a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl +++ b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sort/sortnet/sortnet_tb.pkg.vhdl b/tb/sort/sortnet/sortnet_tb.pkg.vhdl index 16cdfab25..1f9d207fb 100644 --- a/tb/sort/sortnet/sortnet_tb.pkg.vhdl +++ b/tb/sort/sortnet/sortnet_tb.pkg.vhdl @@ -1,7 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- From 55b0c947b822402958e58e06907a8eecc2043f33 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Fri, 19 Jun 2026 14:09:53 +0200 Subject: [PATCH 09/18] remove temporary script for cleanup --- rename_strings.sh | 155 ---------------------------------------------- 1 file changed, 155 deletions(-) delete mode 100644 rename_strings.sh diff --git a/rename_strings.sh b/rename_strings.sh deleted file mode 100644 index 35b4994c4..000000000 --- a/rename_strings.sh +++ /dev/null @@ -1,155 +0,0 @@ -#!/usr/bin/env bash -# -# rename_strings.sh (v4) — recursively replace OLD with NEW both INSIDE FILES -# and in FILE/FOLDER NAMES, for one or more OLD/NEW pairs. Matching of OLD is -# CASE-INSENSITIVE; the result is written in the exact casing of NEW. Case-only -# changes (e.g. addw -> ADDW) are supported. -# -# Usage: -# ./rename_strings.sh [options] OLD1 NEW1 [OLD2 NEW2 ...] -# -n, --dry-run show what would change, modify nothing -# --names-only only rename files/folders (skip file contents) -# --content-only only edit file contents (skip renaming) -# -# Example: -# ./rename_strings.sh cache_TagUnit_Par cache_TagUnit_Parallel addw Adder_Wide -# -# Safeguards (stop a partial match like cache_TagUnit_Par -> ..._Parallel from -# being applied twice): -# * Contents: an occurrence is replaced only when it is NOT already the start -# of NEW (negative lookahead on NEW's trailing part). A file can therefore -# contain both OLD and NEW; only the OLD ones change. -# * Names: an entry whose name already contains NEW is skipped. The name -# check is case-insensitive for a normal pair (an already-NEW name in any -# casing is protected) and case-sensitive for a case-only pair (so the -# files actually get re-cased). -# Binaries and .git are skipped. Files with no real change are not rewritten. -# -# Requires bash >= 4 and perl. - -set -uo pipefail -shopt -s nocasematch - -# Fail clearly on a bash too old for case-insensitive ${var//...} (e.g. macOS -# system bash 3.2) instead of silently skipping files. -_probe="ABC" -if [[ "${_probe//abc/X}" != "X" ]]; then - echo "error: this bash lacks case-insensitive \${var//...}; use bash >= 4." >&2 - exit 1 -fi -command -v perl >/dev/null || { echo "error: perl is required." >&2; exit 1; } - -dry_run=0 -do_names=1 -do_content=1 -while [[ "${1:-}" == -* ]]; do - case "$1" in - -n|--dry-run) dry_run=1 ;; - --names-only) do_content=0 ;; - --content-only) do_names=0 ;; - --) shift; break ;; - *) echo "unknown option: $1" >&2; exit 1 ;; - esac - shift -done - -if [[ $do_names -eq 0 && $do_content -eq 0 ]]; then - echo "error: --names-only and --content-only are mutually exclusive." >&2 - exit 1 -fi -if [[ $# -lt 2 || $(( $# % 2 )) -ne 0 ]]; then - echo "Usage: $0 [-n|--dry-run] [--names-only|--content-only] OLD1 NEW1 ..." >&2 - exit 1 -fi - -# perl program: build a case-insensitive regex for OLD. If LOOK=1, add a -# negative lookahead on SUF so an already-NEW occurrence is left alone. -read -r -d '' PERL_SUBST <<'PERL' || true -BEGIN { $o = $ENV{OLD}; $s = $ENV{SUF}; $n = $ENV{NEW}; - $re = ($ENV{LOOK} eq "1") ? qr/\Q$o\E(?!\Q$s\E)/i : qr/\Q$o\E/i; } -s/$re/$n/g; -PERL -read -r -d '' PERL_COUNT <<'PERL' || true -BEGIN { $o = $ENV{OLD}; $s = $ENV{SUF}; - $re = ($ENV{LOOK} eq "1") ? qr/\Q$o\E(?!\Q$s\E)/i : qr/\Q$o\E/i; } -my $c = () = /$re/g; print $c; -PERL - -while [[ $# -ge 2 ]]; do - old=$1 - new=$2 - shift 2 - - if [[ -z "$old" ]]; then - echo "skip: empty OLD string" >&2 - continue - fi - # True duplicate (byte-identical) -> nothing to do. [ = ] stays - # case-sensitive regardless of nocasematch, so a case-only pair is kept. - if [ "$old" = "$new" ]; then - echo "skip: OLD == NEW ('$old')" >&2 - continue - fi - - # Lookahead only when NEW is strictly longer than OLD and starts with OLD - # (case-insensitively) -- the prefix-collision case (Par -> Parallel). - suffix="" - look=0 - old_lc=${old,,} - new_lc=${new,,} - if [[ ${#new} -gt ${#old} && "${new_lc:0:${#old}}" == "$old_lc" ]]; then - suffix=${new:${#old}} - look=1 - fi - - echo "== pair: '$old' -> '$new' (case-insensitive match) ==" - - # ---- contents ---- - if [[ $do_content -eq 1 ]]; then - # -I skips binaries, -i case-insensitive, -F literal OLD, -Z null output. - grep -rlIiFZ --exclude-dir=.git -e "$old" . 2>/dev/null | - while IFS= read -r -d '' file; do - n=$(OLD="$old" SUF="$suffix" LOOK="$look" perl -0777 -ne "$PERL_COUNT" "$file" 2>/dev/null) - n=${n:-0} - [[ "$n" =~ ^[0-9]+$ ]] || n=0 - [[ "$n" -gt 0 ]] || continue # only already-NEW occurrences: skip rewrite - if [[ $dry_run -eq 1 ]]; then - printf 'edit (dry): %s replacement(s) in %s\n' "$n" "$file" - else - OLD="$old" NEW="$new" SUF="$suffix" LOOK="$look" \ - perl -0777 -i -pe "$PERL_SUBST" "$file" && - printf 'edited: %s replacement(s) in %s\n' "$n" "$file" - fi - done - fi - - # ---- names ---- - if [[ $do_names -eq 1 ]]; then - # Name-safeguard sensitivity: case-sensitive for a case-only pair (so files - # get re-cased), case-insensitive otherwise (protect already-NEW names). - if [[ "$old" == "$new" ]]; then - guard_flags=(-qF) - else - guard_flags=(-qiF) - fi - # -depth: rename children before parents. -iname: match basename, any case. - find . -depth -not -path './.git/*' -iname "*$old*" -print0 | - while IFS= read -r -d '' path; do - base=$(basename "$path") - if printf '%s' "$base" | grep "${guard_flags[@]}" -e "$new"; then - continue - fi - newbase=${base//"$old"/"$new"} - newpath="$(dirname "$path")/$newbase" - if [[ -e "$newpath" ]]; then - echo "skip: target already exists: $newpath" >&2 - continue - fi - if [[ $dry_run -eq 1 ]]; then - printf 'rename (dry): %s -> %s\n' "$path" "$newpath" - else - mv -- "$path" "$newpath" && printf 'renamed: %s -> %s\n' "$path" "$newpath" - fi - done - fi -done From 8c1af97b192277e0e34bc11b3d1d9d666b301f6e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 14:26:06 +0200 Subject: [PATCH 10/18] Cleaned up more findings found by Sigasi. --- src/arith/arith.pkg.vhdl | 18 +++--- src/arith/arith_SquareRoot.vhdl | 18 +++--- src/arith/xilinx/arith_cca_xilinx.vhdl | 10 ++-- src/bus/axi4/axi4_Full.pkg.vhdl | 56 +++++++++---------- src/bus/axi4/axi4_Sink.vhdl | 4 +- src/bus/axi4lite/axi4lite.pkg.vhdl | 30 +++++----- src/bus/axi4lite/axi4lite_OCRAM_Adapter.vhdl | 2 +- src/bus/axi4lite/axi4lite_Register.vhdl | 22 ++++---- src/bus/axi4lite/axi4lite_UART.vhdl | 8 +-- .../axi4stream/axi4stream_FIFO_TempGot.vhdl | 6 +- .../axi4stream/axi4stream_FIFO_TempPut.vhdl | 8 +-- src/bus/bus_Arbiter.vhdl | 3 - src/bus/drp/drp.pkg.vhdl | 8 +-- src/bus/stream/stream.pkg.vhdl | 8 +-- src/bus/stream/stream_DeMux.vhdl | 3 - src/bus/stream/stream_FIFO.vhdl | 4 -- src/bus/stream/stream_FrameGenerator.vhdl | 4 +- src/bus/stream/stream_Mirror.vhdl | 3 - src/cache/cache_CPU.vhdl | 2 +- src/cache/cache_Memory.vhdl | 3 - src/cache/cache_Parallel.vhdl | 2 - src/cache/cache_Parallel2.vhdl | 5 -- src/cache/cache_ReplacementPolicy.vhdl | 21 +++---- src/cache/cache_TagUnit_Parallel.vhdl | 2 - src/cache/cache_TagUnit_Sequential.vhdl | 2 - src/comm/comm.pkg.vhdl | 34 ++++++----- src/common/math.vhdl | 2 +- src/common/physical.vhdl | 4 +- src/common/strings.vhdl | 1 - src/common/utils.vhdl | 1 - src/common/vectors.vhdl | 6 +- src/dstruct/dstruct_Stack.vhdl | 1 - src/fifo/fifo_Stage.vhdl | 4 ++ src/fifo/fifo_cc_got_tempgot.vhdl | 2 +- src/io/ddrio/ddrio_In.vhdl | 2 +- src/io/ddrio/ddrio_InOut.vhdl | 2 +- src/io/ddrio/ddrio_Out.vhdl | 2 +- src/io/io.pkg.vhdl | 21 ++++--- src/io/io_FrequencyCounter.vhdl | 1 - src/io/io_GlitchFilter.vhdl | 22 ++++---- src/io/io_TimingCounter.vhdl | 6 +- src/io/uart/uart.pkg.vhdl | 4 +- src/io/uart/uart_FT245.vhdl | 54 +++++++++--------- src/mem/mem.pkg.vhdl | 2 +- src/mem/ocram/ocram.pkg.vhdl | 20 ++++--- src/mem/ocrom/ocrom.pkg.vhdl | 29 +++++----- src/net/arp/arp_BroadCast_Receiver.vhdl | 4 +- .../arith_SquareRoot_TestHarness.vhdl | 2 +- 48 files changed, 218 insertions(+), 260 deletions(-) diff --git a/src/arith/arith.pkg.vhdl b/src/arith/arith.pkg.vhdl index 61681faa2..d930486fd 100644 --- a/src/arith/arith.pkg.vhdl +++ b/src/arith/arith.pkg.vhdl @@ -137,16 +137,16 @@ package arith is end component; component arith_SquareRoot - generic ( - BITS : positive + generic( + BITS : positive ); - port ( - Clock : in std_logic; - Reset : in std_logic; - Operand : in std_logic_vector(BITS-1 downto 0); - Start : in std_logic; - Result : out std_logic_vector((BITS-1)/2 downto 0); - Ready : out std_logic + port( + Clock : in std_logic; + Reset : in std_logic; + Radicand : in std_logic_vector(BITS-1 downto 0); + Start : in std_logic; + Result : out std_logic_vector((BITS-1)/2 downto 0); + Ready : out std_logic ); end component; diff --git a/src/arith/arith_SquareRoot.vhdl b/src/arith/arith_SquareRoot.vhdl index 30a86c577..5bcb0c8e9 100644 --- a/src/arith/arith_SquareRoot.vhdl +++ b/src/arith/arith_SquareRoot.vhdl @@ -34,22 +34,22 @@ use IEEE.numeric_std.all; entity arith_SquareRoot is generic ( - BITS : positive -- := 8 -- Bit Width of Argument + BITS : positive -- Bit Width of Argument ); port ( -- Global Control - Reset : in std_logic; -- Reset (synchronous) - Clock : in std_logic; -- Clock + Clock : in std_logic; -- Clock + Reset : in std_logic; -- Reset (synchronous) -- Inputs - Operand : in std_logic_vector(BITS-1 downto 0); -- Radicand - Start : in std_logic; -- Start Strobe + Radicand : in std_logic_vector(BITS-1 downto 0); -- Radicand + Start : in std_logic; -- Start Strobe -- Outputs - Result : out std_logic_vector((BITS-1)/2 downto 0); -- Result - Ready : out std_logic -- Ready / Done + Result : out std_logic_vector((BITS-1)/2 downto 0); -- Result + Ready : out std_logic -- Ready / Done ); -end entity arith_SquareRoot; +end entity; architecture rtl of arith_SquareRoot is @@ -83,7 +83,7 @@ begin -- rtl if Start = '1' then -- Initilize Computation - Rmd <= (Rmd'left downto BITS => '0') & unsigned(Operand); + Rmd <= (Rmd'left downto BITS => '0') & unsigned(Radicand); Vld <= (others => '1'); elsif Vld(Vld'left) = '1' then diff --git a/src/arith/xilinx/arith_cca_xilinx.vhdl b/src/arith/xilinx/arith_cca_xilinx.vhdl index cc7da7cd8..560f99169 100644 --- a/src/arith/xilinx/arith_cca_xilinx.vhdl +++ b/src/arith/xilinx/arith_cca_xilinx.vhdl @@ -70,11 +70,10 @@ architecture rtl of arith_cca is function compact return tLevels is variable res : tLevels(0 to 31); - variable base, core, done : integer; + variable base : integer := 0; + variable core : integer := (BITS - L) / 2; + variable done : integer := BITS - 2*core; begin - base := 0; - core := (BITS-L)/2; - done := BITS-2*core; for i in res'range loop res(i) := (base, core, done); if core <= 0 then @@ -92,8 +91,9 @@ architecture rtl of arith_cca is end if; end loop; end function compact; + constant LEVELS : tLevels := compact; - constant CCA : boolean := LEVELS'length > 1; + constant CCA : boolean := LEVELS'length > 1; begin genRCA: if not CCA generate diff --git a/src/bus/axi4/axi4_Full.pkg.vhdl b/src/bus/axi4/axi4_Full.pkg.vhdl index a1564edcf..5763c8ef2 100644 --- a/src/bus/axi4/axi4_Full.pkg.vhdl +++ b/src/bus/axi4/axi4_Full.pkg.vhdl @@ -170,8 +170,8 @@ package axi4_Full is function IDResize(InBus : T_AXI4_Bus_M2S; AWIDBits : natural; ARIDBits : natural) return T_AXI4_Bus_M2S; function IDResize(InBus : T_AXI4_Bus_S2M; RIDBits : natural; BIDBits : natural) return T_AXI4_Bus_S2M; - function Initialize_AXI4_Bus_S2M(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_S2M; function Initialize_AXI4_Bus_M2S(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_M2S; + function Initialize_AXI4_Bus_S2M(DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_S2M; procedure ConnectAndResize(signal In_M2S : in T_AXI4_Bus_M2S; signal In_S2M : out T_AXI4_Bus_S2M; signal Out_M2S : out T_AXI4_Bus_M2S; signal Out_S2M : in T_AXI4_Bus_S2M; constant Info_Prefix : string := ""); type T_AXI4_Bus is record @@ -634,32 +634,8 @@ package body axi4_Full is return temp; end function; - function Initialize_AXI4_Bus_S2M(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_S2M is - variable var : T_AXI4_Bus_S2M( - BID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), RID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), - BUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), RUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), - RData(DataBits - 1 downto 0) - ) := ( - AWReady => Value, - WReady => Value, - BValid => Value, - BResp => (others => Value), - BID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), - BUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), - ARReady => Value, - RValid => Value, - RData => (DataBits - 1 downto 0 => Value), - RResp => (others => Value), - RID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), - RLast => Value, - RUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value) - ); - begin - return var; - end function; - function Initialize_AXI4_Bus_M2S(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_M2S is - variable var : T_AXI4_Bus_M2S( + constant init : T_AXI4_Bus_M2S( AWID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), ARID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), AWUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), ARUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), WUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), WData(DataBits - 1 downto 0), WStrb((DataBits / 8) - 1 downto 0), @@ -698,14 +674,38 @@ package body axi4_Full is RReady => Value ); begin - return var; + return init; + end function; + + function Initialize_AXI4_Bus_S2M(DataBits : natural; UserBits : natural := 0; IDBits : natural := 0; Value : std_logic := 'Z') return T_AXI4_Bus_S2M is + constant init : T_AXI4_Bus_S2M( + BID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), RID(ite(IDBits = 0, 1, IDBits) - 1 downto 0), + BUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), RUser(ite(UserBits = 0, 1, UserBits) - 1 downto 0), + RData(DataBits - 1 downto 0) + ) := ( + AWReady => Value, + WReady => Value, + BValid => Value, + BResp => (others => Value), + BID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), + BUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value), + ARReady => Value, + RValid => Value, + RData => (DataBits - 1 downto 0 => Value), + RResp => (others => Value), + RID => (ite(IDBits = 0, 1, IDBits) - 1 downto 0 => Value), + RLast => Value, + RUser => (ite(UserBits = 0, 1, UserBits) - 1 downto 0 => Value) + ); + begin + return init; end function; function Initialize_AXI4_Bus(AddressBits : natural; DataBits : natural; UserBits : natural := 0; IDBits : natural := 0) return T_AXI4_Bus is begin return ( M2S => Initialize_AXI4_Bus_M2S(AddressBits, DataBits, UserBits, IDBits), - S2M => Initialize_AXI4_Bus_S2M(AddressBits, DataBits, UserBits, IDBits) + S2M => Initialize_AXI4_Bus_S2M(DataBits, UserBits, IDBits) ); end function; diff --git a/src/bus/axi4/axi4_Sink.vhdl b/src/bus/axi4/axi4_Sink.vhdl index 547a9b7b0..4791614f8 100644 --- a/src/bus/axi4/axi4_Sink.vhdl +++ b/src/bus/axi4/axi4_Sink.vhdl @@ -181,9 +181,7 @@ begin nxt_wstate <= Idle; end if; - when others => nxt_wstate <= Idle; - - end case; + end case; end process; read_proc : process (all) diff --git a/src/bus/axi4lite/axi4lite.pkg.vhdl b/src/bus/axi4lite/axi4lite.pkg.vhdl index 59b4dbb90..813f6562d 100644 --- a/src/bus/axi4lite/axi4lite.pkg.vhdl +++ b/src/bus/axi4lite/axi4lite.pkg.vhdl @@ -125,7 +125,7 @@ package axi4lite is type T_axi4lite_Bus_VECTOR is array(natural range <>) of T_axi4lite_Bus; function Initialize_axi4lite_Bus_M2S(AddressBits : natural; DataBits : natural; Value : std_logic := 'Z') return T_AXI4LITE_BUS_M2S; - function Initialize_axi4lite_Bus_S2M(AddressBits : natural; DataBits : natural; Value : std_logic := 'Z') return T_AXI4LITE_BUS_S2M; + function Initialize_axi4lite_Bus_S2M(DataBits : natural; Value : std_logic := 'Z') return T_AXI4LITE_BUS_S2M; function Initialize_axi4lite_Bus(AddressBits : natural; DataBits : natural) return T_axi4lite_Bus; -------Define AXI Register structure------------- @@ -365,7 +365,7 @@ package body axi4lite is end function; function Initialize_axi4lite_Bus_M2S(AddressBits : natural; DataBits : natural; Value : std_logic := 'Z') return T_axi4lite_Bus_M2S is - variable var : T_axi4lite_Bus_M2S( + constant init : T_axi4lite_Bus_M2S( AWAddr(AddressBits - 1 downto 0), WData(DataBits - 1 downto 0), WStrb((DataBits /8) - 1 downto 0), ARAddr(AddressBits - 1 downto 0)) := ( -- AClk => Value, @@ -385,11 +385,11 @@ package body axi4lite is RReady => Value ); begin - return var; + return init; end function; - function Initialize_axi4lite_Bus_S2M(AddressBits : natural; DataBits : natural; Value : std_logic := 'Z') return T_axi4lite_Bus_S2M is - variable var : T_axi4lite_Bus_S2M(RData(DataBits - 1 downto 0)) := ( + function Initialize_axi4lite_Bus_S2M(DataBits : natural; Value : std_logic := 'Z') return T_axi4lite_Bus_S2M is + constant init : T_axi4lite_Bus_S2M(RData(DataBits - 1 downto 0)) := ( AWReady => Value, WReady => Value, BValid => Value, @@ -400,14 +400,14 @@ package body axi4lite is RResp => (others => Value) ); begin - return var; + return init; end function; function Initialize_axi4lite_Bus(AddressBits : natural; DataBits : natural) return T_axi4lite_Bus is begin return ( M2S => Initialize_axi4lite_Bus_M2S(AddressBits, DataBits), - S2M => Initialize_axi4lite_Bus_S2M(AddressBits, DataBits) + S2M => Initialize_axi4lite_Bus_S2M(DataBits) ); end function; @@ -421,8 +421,6 @@ package body axi4lite is end function; impure function write_csv_file(FileName : string; reg : T_AXI4_Register_Vector) return boolean is - constant QM : character := '"'; - constant size_header : natural := imax(FileName'length, 51); file FileHandle : TEXT open write_MODE is FileName; variable CurrentLine : LINE; @@ -547,7 +545,7 @@ package body axi4lite is AutoClear_Mask : std_logic_vector(DATA_BITS - 1 downto 0) := (others => '0'); IsInterruptRegister : boolean := false ) return T_AXI4_Register is - variable temp : T_AXI4_Register := ( + constant init : T_AXI4_Register := ( Name => resize(Name, NAME_LENGTH), Address => Address, RegisterMode => RegisterMode, @@ -556,7 +554,7 @@ package body axi4lite is IsInterruptRegister => IsInterruptRegister ); begin - return temp; + return init; end function; procedure assign( @@ -836,12 +834,10 @@ package body axi4lite is constant T_reg : in std_logic_vector(DATA_BITS - 1 downto 0); signal nextT_reg : out std_logic_vector(DATA_BITS - 1 downto 0) ) is - constant Value_idx : natural := 0; - constant BitSet_idx : natural := 1; - constant BitClr_idx : natural := 2; - constant BitTgl_idx : natural := 3; - - variable newValue : std_logic_vector(DATA_BITS - 1 downto 0); + -- constant Value_idx : natural := 0; + -- constant BitSet_idx : natural := 1; + -- constant BitClr_idx : natural := 2; + -- constant BitTgl_idx : natural := 3; begin --IO Register Output <= IO_reg; diff --git a/src/bus/axi4lite/axi4lite_OCRAM_Adapter.vhdl b/src/bus/axi4lite/axi4lite_OCRAM_Adapter.vhdl index 2ba67e640..09ce6da2b 100644 --- a/src/bus/axi4lite/axi4lite_OCRAM_Adapter.vhdl +++ b/src/bus/axi4lite/axi4lite_OCRAM_Adapter.vhdl @@ -180,7 +180,7 @@ begin nextState <= st_await_write_data; when "011" | "101" | "111" => -- read and write address at the same time - if (PREFFERED_READ_ACCESS = TRUE) then + if PREFFERED_READ_ACCESS then nextAddress <= unsigned(AXI4L_m2s_int.ARAddr(OCRAM_ADDRESS_BITS + ADDR_LSB -1 downto ADDR_LSB)); nextState <= st_read_data_ack; diff --git a/src/bus/axi4lite/axi4lite_Register.vhdl b/src/bus/axi4lite/axi4lite_Register.vhdl index 1e303d1b6..98838b275 100644 --- a/src/bus/axi4lite/axi4lite_Register.vhdl +++ b/src/bus/axi4lite/axi4lite_Register.vhdl @@ -475,15 +475,16 @@ begin -- Output register or memory read data process(Clock) is - function first_out(slv : std_logic_vector; reg : T_SLVV) return std_logic_vector is - begin - for i in slv'low to slv'high loop - if (slv(i)) = '1' then - return reg(i); - end if; - end loop; - return reg(0); - end function; + -- function first_out(slv : std_logic_vector; reg : T_SLVV) return std_logic_vector is + -- begin + -- for i in slv'low to slv'high loop + -- if (slv(i)) = '1' then + -- return reg(i); + -- end if; + -- end loop; + -- return reg(0); + -- end function; + function lssb_idx_with_loop(slv : std_logic_vector) return integer is begin for i in slv'low to slv'high loop @@ -493,6 +494,7 @@ begin end loop; return 0; end function; + variable idx : integer; begin if (rising_edge (Clock)) then @@ -542,7 +544,7 @@ begin ------------ Address Hit's --------------------------- - high_addr_gen : if (REG_ADDRESS_BITS >= ADDRESS_BITS) or (IGNORE_HIGH_ADDRESS = TRUE) generate + high_addr_gen : if (REG_ADDRESS_BITS >= ADDRESS_BITS) or IGNORE_HIGH_ADDRESS generate is_high_r <= '1'; is_high_w <= '1'; else generate diff --git a/src/bus/axi4lite/axi4lite_UART.vhdl b/src/bus/axi4lite/axi4lite_UART.vhdl index 5226887a5..021c6cbc0 100644 --- a/src/bus/axi4lite/axi4lite_UART.vhdl +++ b/src/bus/axi4lite/axi4lite_UART.vhdl @@ -95,8 +95,6 @@ architecture rtl of axi4lite_UART is --user required axi registers signal RX_Data : std_logic_vector(7 downto 0); signal TX_Data : std_logic_vector(7 downto 0); - signal Status : std_logic_vector(31 downto 0); - signal Control : std_logic_vector(31 downto 0); --Bit positions of the above registers signal Status_RX_Valid : std_logic; @@ -119,8 +117,6 @@ architecture rtl of axi4lite_UART is signal Control_TX_Reset : std_logic; signal Control_InterruptEnable : std_logic; - signal Status_TX_EmptyState : std_logic_vector(imax(0, TX_EMPTY_STATE_BITS - 1) downto 0); - signal Status_RX_FillState : std_logic_vector(imax(0, RX_FILL_STATE_BITS - 1) downto 0); begin Reg : entity work.axi4lite_Register generic map( @@ -205,13 +201,13 @@ begin TX_Put => TX_Put, TX_Data => TX_Data, TX_Full => Status_TX_Full, - TX_EmptyState => Status_TX_EmptyState, + TX_EmptyState => open, TXFIFO_Reset => Control_TX_Reset, TXFIFO_Empty => TXFIFO_Empty, RX_Valid => Status_RX_Valid, RX_Data => RX_Data, RX_Got => RX_Got, - RX_FillState => Status_RX_FillState, + RX_FillState => open, RX_Overflow => RX_OverFlow, RXFIFO_Full => Status_RX_Full, RXFIFO_Reset => Control_RX_Reset, diff --git a/src/bus/axi4stream/axi4stream_FIFO_TempGot.vhdl b/src/bus/axi4stream/axi4stream_FIFO_TempGot.vhdl index fc62688d5..419bde943 100644 --- a/src/bus/axi4stream/axi4stream_FIFO_TempGot.vhdl +++ b/src/bus/axi4stream/axi4stream_FIFO_TempGot.vhdl @@ -100,16 +100,12 @@ architecture rtl of axi4stream_FIFO_TempGot is signal DataFIFO_DataOut : std_logic_vector(DataFIFO_DataIn'range); signal DataFIFO_Valid : std_logic; - signal FrameCommit : std_logic; - - signal In_SOF : std_logic; signal started : std_logic := '0'; signal Out_M2S_i : In_m2s'subtype; begin - In_SOF <= In_m2s.Valid and not started; - started <= ffrs(q => started, rst => ((In_m2s.Valid and In_m2s.Last) or Reset), set => (In_m2s.Valid)) when rising_edge(Clock); + started <= ffrs(q => started, rst => ((In_m2s.Valid and In_m2s.Last) or Reset), set => (In_m2s.Valid)) when rising_edge(Clock); process(Clock) begin diff --git a/src/bus/axi4stream/axi4stream_FIFO_TempPut.vhdl b/src/bus/axi4stream/axi4stream_FIFO_TempPut.vhdl index 0be119977..fc58bcd75 100644 --- a/src/bus/axi4stream/axi4stream_FIFO_TempPut.vhdl +++ b/src/bus/axi4stream/axi4stream_FIFO_TempPut.vhdl @@ -117,17 +117,15 @@ architecture rtl of axi4stream_FIFO_TempPut is signal DataFIFO_DataOut : std_logic_vector(DataFIFO_DataIn'range); signal DataFIFO_Valid : std_logic; - signal In_SOF : std_logic; - signal started : std_logic := '0'; + signal started : std_logic := '0'; --We set the ranges of Out_S2M_i manually to the values from input to force the input and output record to be the same sizes. - signal Out_M2S_i : T_AXI4Stream_M2S(Data(DATA_BITS -1 downto 0), Keep(DATA_BITS /8 -1 downto 0), User(USER_BITS -1 downto 0), ID(ID_BITS-1 downto 0), DEST(DEST_BITS-1 downto 0)); + signal Out_M2S_i : T_AXI4Stream_M2S(Data(DATA_BITS -1 downto 0), Keep(DATA_BITS /8 -1 downto 0), User(USER_BITS -1 downto 0), ID(ID_BITS-1 downto 0), DEST(DEST_BITS-1 downto 0)); begin assert not NO_META_FIFO report "PoC.axi4stream_FIFO_TempPut:: NO_META_FIFO is set. Meta Fifo is removed! Dest, ID and, depending on USER_IS_DYNAMIC, User is removed" severity warning; - In_SOF <= In_M2S.Valid and not started; - started <= ffrs(q => started, rst => ((In_M2S.Valid and In_M2S.Last) or Reset), set => (In_M2S.Valid)) when rising_edge(Clock); + started <= ffrs(q => started, rst => ((In_M2S.Valid and In_M2S.Last) or Reset), set => (In_M2S.Valid)) when rising_edge(Clock); process(Clock) begin diff --git a/src/bus/bus_Arbiter.vhdl b/src/bus/bus_Arbiter.vhdl index b4b05ca63..f23985d35 100644 --- a/src/bus/bus_Arbiter.vhdl +++ b/src/bus/bus_Arbiter.vhdl @@ -56,9 +56,6 @@ entity bus_Arbiter is ); end entity; architecture rtl of bus_Arbiter is - attribute KEEP : boolean; - attribute FSM_ENCODING : string; - begin -- XXX: How does arith_FirstOne relate to an arbiter and to RR or Priority arbitration? gen_Strategy : if STRATEGY = "RR" generate -- Round Robin Arbiter diff --git a/src/bus/drp/drp.pkg.vhdl b/src/bus/drp/drp.pkg.vhdl index c493c8d48..62cd0014c 100644 --- a/src/bus/drp/drp.pkg.vhdl +++ b/src/bus/drp/drp.pkg.vhdl @@ -64,7 +64,7 @@ end package; package body drp is function Initialize_DRP_Bus_M2S(AddressBits : natural; DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus_M2S is - variable var : T_DRP_Bus_M2S( + constant init : T_DRP_Bus_M2S( Address(AddressBits -1 downto 0), DataIn(DataBits -1 downto 0) ) :=( @@ -74,16 +74,16 @@ package body drp is DataIn => (DataBits - 1 downto 0 => Value) ); begin - return var; + return init; end function; function Initialize_DRP_Bus_S2M(DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus_S2M is - variable var : T_DRP_Bus_S2M(DataOut(DataBits -1 downto 0)) :=( + constant init : T_DRP_Bus_S2M(DataOut(DataBits -1 downto 0)) :=( Ready => Value, DataOut => (DataBits - 1 downto 0 => Value) ); begin - return var; + return init; end function; function Initialize_DRP_Bus(AddressBits : natural; DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus is diff --git a/src/bus/stream/stream.pkg.vhdl b/src/bus/stream/stream.pkg.vhdl index e15bac146..8efee057f 100644 --- a/src/bus/stream/stream.pkg.vhdl +++ b/src/bus/stream/stream.pkg.vhdl @@ -567,7 +567,7 @@ package body stream is end function; function to_flag1_string(stmw : T_SIM_STREAM_WORD_8) return string is - variable flag : std_logic_vector(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; + constant flag : std_logic_vector(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; begin case flag is when "000" => return ""; @@ -583,7 +583,7 @@ package body stream is end function; function to_flag1_string(stmw : T_SIM_STREAM_WORD_32) return string is - variable flag : std_logic_vector(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; + constant flag : std_logic_vector(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; begin case flag is when "000" => return ""; @@ -599,7 +599,7 @@ package body stream is end function; function to_flag2_string(stmw : T_SIM_STREAM_WORD_8) return string is - variable flag : std_logic_vector(1 downto 0) := stmw.Ready & stmw.Valid; + constant flag : std_logic_vector(1 downto 0) := stmw.Ready & stmw.Valid; begin case flag is when "00" => return " "; @@ -613,7 +613,7 @@ package body stream is end function; function to_flag2_string(stmw : T_SIM_STREAM_WORD_32) return string is - variable flag : std_logic_vector(1 downto 0) := stmw.Ready & stmw.Valid; + constant flag : std_logic_vector(1 downto 0) := stmw.Ready & stmw.Valid; begin case flag is when "00" => return " "; diff --git a/src/bus/stream/stream_DeMux.vhdl b/src/bus/stream/stream_DeMux.vhdl index 592aa104c..2aa031039 100644 --- a/src/bus/stream/stream_DeMux.vhdl +++ b/src/bus/stream/stream_DeMux.vhdl @@ -67,9 +67,6 @@ end entity; architecture rtl of stream_DeMux is - attribute KEEP : boolean; - attribute FSM_ENCODING : string; - subtype T_CHANNEL_INDEX is natural range 0 to PORTS - 1; type T_STATE is (ST_IDLE, ST_DATAFLOW, ST_DISCARD_FRAME); diff --git a/src/bus/stream/stream_FIFO.vhdl b/src/bus/stream/stream_FIFO.vhdl index 259e53801..75e0ce456 100644 --- a/src/bus/stream/stream_FIFO.vhdl +++ b/src/bus/stream/stream_FIFO.vhdl @@ -72,10 +72,6 @@ end entity; architecture rtl of stream_FIFO is - attribute FSM_ENCODING : string; - - constant META_STREAMS : positive := META_BITS'length; - type T_WRITER_STATE is (ST_IDLE, ST_FRAME); type T_READER_STATE is (ST_IDLE, ST_FRAME); diff --git a/src/bus/stream/stream_FrameGenerator.vhdl b/src/bus/stream/stream_FrameGenerator.vhdl index 435c0622d..ba43aaf86 100644 --- a/src/bus/stream/stream_FrameGenerator.vhdl +++ b/src/bus/stream/stream_FrameGenerator.vhdl @@ -82,7 +82,7 @@ architecture rtl of stream_FrameGenerator is signal ContentCounter_en : std_logic; signal ContentCounter_us : unsigned(WORD_BITS - 1 downto 0) := (others => '0'); - signal PRNG_rst : std_logic; + signal PRNG_rst : std_logic; -- FIXME: Why is reset not driven by FSM anymore? signal PRNG_got : std_logic; signal PRNG_Data : std_logic_vector(DATA_BITS - 1 downto 0); begin @@ -147,8 +147,6 @@ begin when FRAMEGEN_CMD_ALL_FRAMES => NextState <= ST_ERROR; - when others => - NextState <= ST_ERROR; end case; -- generate sequential numbers diff --git a/src/bus/stream/stream_Mirror.vhdl b/src/bus/stream/stream_Mirror.vhdl index 04d5e47b2..43b988b20 100644 --- a/src/bus/stream/stream_Mirror.vhdl +++ b/src/bus/stream/stream_Mirror.vhdl @@ -65,9 +65,6 @@ entity stream_Mirror is ); end entity; architecture rtl of stream_Mirror is - attribute KEEP : boolean; - attribute FSM_ENCODING : string; - signal FifoStage_put : std_logic; signal FifoStage_DataIn : std_logic_vector(DATA_BITS + 1 downto 0); signal FifoStage_Full : std_logic; diff --git a/src/cache/cache_CPU.vhdl b/src/cache/cache_CPU.vhdl index 9e3ae4a2a..c3ce8125a 100644 --- a/src/cache/cache_CPU.vhdl +++ b/src/cache/cache_CPU.vhdl @@ -395,7 +395,7 @@ begin -- architecture rtl fsm_ns <= UNKNOWN; cpu_Got <= 'X'; cache_Request <= 'X'; - cache_ReadWrite <= 'X'; + cache_ReadWrite <= 'X'; cache_Invalidate <= 'X'; cache_Replace <= 'X'; end case; diff --git a/src/cache/cache_Memory.vhdl b/src/cache/cache_Memory.vhdl index be522a169..a1efd0012 100644 --- a/src/cache/cache_Memory.vhdl +++ b/src/cache/cache_Memory.vhdl @@ -218,9 +218,6 @@ begin signal cpu_addr_r : unsigned(CPU_ADDR_BITS-1 downto 0); signal cpu_wdata_r : std_logic_vector(CPU_DATA_BITS-1 downto 0); signal cpu_wmask_r : std_logic_vector(CPU_DATA_BITS/8-1 downto 0); - signal cpu_rdy_r : std_logic; - signal cpu_rstb_r : std_logic; - signal cpu_rdata_r : std_logic_vector(CPU_DATA_BITS-1 downto 0); begin -- cpu_rdy should have a short clock-to-output delay, but int_got has a large -- propagation delay. Thus, do not depend cpu_rdy and int_got. diff --git a/src/cache/cache_Parallel.vhdl b/src/cache/cache_Parallel.vhdl index 33d3d9266..a0d60aa6f 100644 --- a/src/cache/cache_Parallel.vhdl +++ b/src/cache/cache_Parallel.vhdl @@ -112,8 +112,6 @@ end entity; architecture rtl of cache_Parallel is - attribute KEEP : boolean; - constant LINE_INDEX_BITS : positive := log2ceilnz(CACHE_LINES); subtype T_CACHE_LINE is std_logic_vector(DATA_BITS - 1 downto 0); diff --git a/src/cache/cache_Parallel2.vhdl b/src/cache/cache_Parallel2.vhdl index f5d7c8a0f..7dd466403 100644 --- a/src/cache/cache_Parallel2.vhdl +++ b/src/cache/cache_Parallel2.vhdl @@ -146,13 +146,8 @@ end entity; architecture rtl of cache_Parallel2 is - attribute KEEP : boolean; - constant LINE_INDEX_BITS : positive := log2ceilnz(CACHE_LINES); - subtype T_CACHE_LINE is std_logic_vector(DATA_BITS - 1 downto 0); - type T_CACHE_LINE_VECTOR is array (natural range <>) of T_CACHE_LINE; -- FIXME: T_SLVV - -- look-up (request) signal TU_LineIndex : std_logic_vector(LINE_INDEX_BITS - 1 downto 0); signal TU_TagHit : std_logic; diff --git a/src/cache/cache_ReplacementPolicy.vhdl b/src/cache/cache_ReplacementPolicy.vhdl index 8bb1e4be0..41abe6fc8 100644 --- a/src/cache/cache_ReplacementPolicy.vhdl +++ b/src/cache/cache_ReplacementPolicy.vhdl @@ -101,11 +101,6 @@ end entity; architecture rtl of cache_ReplacementPolicy is - attribute KEEP : boolean; - attribute FSM_ENCODING : string; - - constant KEY_BITS : positive := log2ceilnz(CACHE_WAYS); - begin assert (str_equal(REPLACEMENT_POLICY, "RR") or str_equal(REPLACEMENT_POLICY, "LRU")) @@ -117,17 +112,17 @@ begin -- policy: RR - round robin -- =========================================================================== genRR : if str_equal(REPLACEMENT_POLICY, "RR") generate - constant VALID_BIT : natural := 0; + -- constant VALID_BIT : natural := 0; - subtype T_OPTION_LINE is std_logic_vector(0 downto 0); - type T_OPTION_LINE_VECTOR is array (natural range <>) of T_OPTION_LINE; + -- subtype T_OPTION_LINE is std_logic_vector(0 downto 0); + -- type T_OPTION_LINE_VECTOR is array (natural range <>) of T_OPTION_LINE; - signal OptionMemory : T_OPTION_LINE_VECTOR(CACHE_WAYS - 1 downto 0) := (others => ( - VALID_BIT => '0') - ); + -- signal OptionMemory : T_OPTION_LINE_VECTOR(CACHE_WAYS - 1 downto 0) := (others => ( + -- VALID_BIT => '0') + -- ); - signal ValidHit : std_logic; - signal Pointer_us : unsigned(log2ceilnz(CACHE_WAYS) - 1 downto 0) := (others => '0'); + -- signal ValidHit : std_logic; + -- signal Pointer_us : unsigned(log2ceilnz(CACHE_WAYS) - 1 downto 0) := (others => '0'); begin -- ValidHit <= OptionMemory(to_integer(unsigned(HitWay)))(VALID_BIT); diff --git a/src/cache/cache_TagUnit_Parallel.vhdl b/src/cache/cache_TagUnit_Parallel.vhdl index 55db1ac9e..e88fc6de4 100644 --- a/src/cache/cache_TagUnit_Parallel.vhdl +++ b/src/cache/cache_TagUnit_Parallel.vhdl @@ -133,8 +133,6 @@ entity cache_TagUnit_Parallel is end entity; architecture rtl of cache_TagUnit_Parallel is - attribute KEEP : boolean; - constant SETS : positive := CACHE_LINES / ASSOCIATIVITY; -- Returns true if unsigned value contains metalogical values. diff --git a/src/cache/cache_TagUnit_Sequential.vhdl b/src/cache/cache_TagUnit_Sequential.vhdl index 33446a6df..8736284fa 100644 --- a/src/cache/cache_TagUnit_Sequential.vhdl +++ b/src/cache/cache_TagUnit_Sequential.vhdl @@ -71,8 +71,6 @@ end entity; architecture rtl of cache_TagUnit_Sequential is - attribute KEEP : boolean; - constant SETS : positive := CACHE_LINES / ASSOCIATIVITY; begin diff --git a/src/comm/comm.pkg.vhdl b/src/comm/comm.pkg.vhdl index f548d4147..205a0de70 100644 --- a/src/comm/comm.pkg.vhdl +++ b/src/comm/comm.pkg.vhdl @@ -30,26 +30,30 @@ library IEEE; use IEEE.std_logic_1164.all; +use work.utils.all; + package comm is -- Calculates the Remainder of the Division by the Generator Polynomial GEN. - component comm_CRC is - generic ( - POLYNOMIAL : bit_vector; -- Generator Polynom - BITS : positive -- Number of Bits to be processed in parallel + component comm_CRC + generic( + POLYNOMIAL : bit_vector; + BITS : positive; + CHUNK_BITS : positive := BITS; + INIT : std_logic_vector := "0"; + OUTPUT_REGS : boolean := true ); - port ( - Clock : in std_logic; -- Clock - - Load : in std_logic; -- Parallel Preload of Remainder - Seed : in std_logic_vector(POLYNOMIAL'length-2 downto 0); -- - Enable : in std_logic; -- Process Input Data (MSB first) - DataIn : in std_logic_vector(BITS-1 downto 0); -- - - Remainder : out std_logic_vector(POLYNOMIAL'length-2 downto 0); -- Remainder - IsZero : out std_logic -- Remainder is Zero + port( + Clock : in std_logic; + Load : in std_logic; + Seed : in std_logic_vector(abs(mssb_idx(POLYNOMIAL)-POLYNOMIAL'right)-1 downto 0); + Enable : in std_logic; + ChunkEnable : in std_logic_vector(CHUNK_BITS-1 downto 0) := (CHUNK_BITS-1 downto 0 => '1'); + DataIn : in std_logic_vector(BITS-1 downto 0); + Remainder : out std_logic_vector(abs(mssb_idx(POLYNOMIAL)-POLYNOMIAL'right)-1 downto 0); + IsZero : out std_logic ); - end component; + end component comm_CRC; -- Computes XOR masks for stream scrambling from an LFSR generator. component comm_Scramble is diff --git a/src/common/math.vhdl b/src/common/math.vhdl index 68089e814..898926393 100644 --- a/src/common/math.vhdl +++ b/src/common/math.vhdl @@ -167,7 +167,7 @@ package body math is constant zeroes : natural_vector(0 to 0) := (others => 0); variable actualNumerator : natural := 1; variable tab : natural := 0; - variable increment : real := fractionalInReal; + constant increment : real := fractionalInReal; variable remainder : real := fractionalInReal; variable result : natural_vector(0 to numerator -1) := (others => 0); begin diff --git a/src/common/physical.vhdl b/src/common/physical.vhdl index 1f136b52b..8efcc9c68 100644 --- a/src/common/physical.vhdl +++ b/src/common/physical.vhdl @@ -320,7 +320,7 @@ package body physical is end if; end if; res := 1.0 / real(f / 1 Hz); - if (POC_VERBOSE = TRUE) then + if POC_VERBOSE then report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note; end if; return res; @@ -425,7 +425,7 @@ package body physical is end if; end if; res := (f / 1 Hz) * 1 Bd; - if (POC_VERBOSE = TRUE) then + if POC_VERBOSE then report "to_baud: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note; end if; return res; diff --git a/src/common/strings.vhdl b/src/common/strings.vhdl index 9952c2e0d..e89960e72 100644 --- a/src/common/strings.vhdl +++ b/src/common/strings.vhdl @@ -215,7 +215,6 @@ package body strings is when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; - when others => return 'X'; end case; end function; diff --git a/src/common/utils.vhdl b/src/common/utils.vhdl index dd4322042..0b4601128 100644 --- a/src/common/utils.vhdl +++ b/src/common/utils.vhdl @@ -1573,7 +1573,6 @@ package body utils is when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE; when ROUND_UP => return integer(ceil(result)); when ROUND_DOWN => return integer(floor(result)); - when others => report "scale: unsupported RoundingStyle." severity FAILURE; end case; return integer(result); end if; diff --git a/src/common/vectors.vhdl b/src/common/vectors.vhdl index aa7733574..4b032eafe 100644 --- a/src/common/vectors.vhdl +++ b/src/common/vectors.vhdl @@ -371,14 +371,14 @@ package body vectors is -- Make vector of constant function genVector(const : std_logic; length : natural) return std_logic_vector is - variable slv : std_logic_vector(length -1 downto 0) := (others => const); -- FIXME: use (length - 1 downto 0 => ...) directly in return statement + constant slv : std_logic_vector(length -1 downto 0) := (others => const); -- FIXME: use (length - 1 downto 0 => ...) directly in return statement begin return slv; end function; -- FIXME: input as std_logic, return an SLVV of that size function genVector(const : std_logic_vector; length : natural) return T_SLVV is - variable slv : T_SLVV(length -1 downto 0)(const'range) := (others => const); -- FIXME: use (length - 1 downto 0 => ...) directly in return statement + constant slv : T_SLVV(length -1 downto 0)(const'range) := (others => const); -- FIXME: use (length - 1 downto 0 => ...) directly in return statement begin return slv; end function; @@ -1477,7 +1477,7 @@ package body vectors is end function; function to_string_bin(slm : T_SLM; groups : positive := 4; format : character := 'h') return string is - variable PerLineOverheader : positive := div_ceil(slm'length(2), groups); + constant PerLineOverheader : positive := div_ceil(slm'length(2), groups); variable Result : string(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10); variable Writer : positive; variable GroupCounter : natural; diff --git a/src/dstruct/dstruct_Stack.vhdl b/src/dstruct/dstruct_Stack.vhdl index a34979270..13b0175e4 100644 --- a/src/dstruct/dstruct_Stack.vhdl +++ b/src/dstruct/dstruct_Stack.vhdl @@ -70,7 +70,6 @@ architecture rtl of dstruct_Stack is signal adr : unsigned(ADDRESS_BITS-1 downto 0) := (others => '0'); signal s_adr : unsigned(ADDRESS_BITS-1 downto 0) := (others => '0'); signal s_dout : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0'); - signal s_valid : std_logic := '0'; signal s_din : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0'); -- ctrl signal for stackpointer operations diff --git a/src/fifo/fifo_Stage.vhdl b/src/fifo/fifo_Stage.vhdl index 90a5bfb0f..eac108050 100644 --- a/src/fifo/fifo_Stage.vhdl +++ b/src/fifo/fifo_Stage.vhdl @@ -104,6 +104,10 @@ begin Full <= Avail and not got_v(i) and (Full or put_v(i)); end if; end if; + end process; + + process (Clock) + begin if rising_edge(Clock) then if Full = '0' then A <= di_v(i); diff --git a/src/fifo/fifo_cc_got_tempgot.vhdl b/src/fifo/fifo_cc_got_tempgot.vhdl index ad47e9762..a27fb11cc 100644 --- a/src/fifo/fifo_cc_got_tempgot.vhdl +++ b/src/fifo/fifo_cc_got_tempgot.vhdl @@ -119,7 +119,7 @@ architecture rtl of fifo_cc_got_tempgot is constant ADDRESS_BITS : natural := log2ceil(MIN_DEPTH); -- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures - constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (ADDRESS_BITS > 4); + -- constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (ADDRESS_BITS > 4); ----------------------------------------------------------------------------- -- Memory Pointers diff --git a/src/io/ddrio/ddrio_In.vhdl b/src/io/ddrio/ddrio_In.vhdl index 34881369c..ec7293639 100644 --- a/src/io/ddrio/ddrio_In.vhdl +++ b/src/io/ddrio/ddrio_In.vhdl @@ -85,7 +85,7 @@ end entity; architecture rtl of ddrio_In is begin - assert ((VENDOR = VENDOR_ALTERA) or ((SIMULATION = TRUE) and (VENDOR = VENDOR_GENERIC)) or (VENDOR = VENDOR_XILINX)) + assert ((VENDOR = VENDOR_ALTERA) or (SIMULATION and (VENDOR = VENDOR_GENERIC)) or (VENDOR = VENDOR_XILINX)) report "PoC.io.ddrio.in is not implemented for given DEVICE." severity FAILURE; diff --git a/src/io/ddrio/ddrio_InOut.vhdl b/src/io/ddrio/ddrio_InOut.vhdl index 8de4ab797..745dd690a 100644 --- a/src/io/ddrio/ddrio_InOut.vhdl +++ b/src/io/ddrio/ddrio_InOut.vhdl @@ -106,7 +106,7 @@ end entity; architecture rtl of ddrio_InOut is begin - assert ((VENDOR = VENDOR_ALTERA) or ((SIMULATION = TRUE) and (VENDOR = VENDOR_GENERIC)) or (VENDOR = VENDOR_XILINX)) + assert ((VENDOR = VENDOR_ALTERA) or (SIMULATION and (VENDOR = VENDOR_GENERIC)) or (VENDOR = VENDOR_XILINX)) report "PoC.io.ddrio.inout is not implemented for given DEVICE." severity FAILURE; diff --git a/src/io/ddrio/ddrio_Out.vhdl b/src/io/ddrio/ddrio_Out.vhdl index ce726e3fa..cc0a869e0 100644 --- a/src/io/ddrio/ddrio_Out.vhdl +++ b/src/io/ddrio/ddrio_Out.vhdl @@ -92,7 +92,7 @@ end entity; architecture rtl of ddrio_Out is begin - assert ((VENDOR = VENDOR_ALTERA) or ((SIMULATION = TRUE) and (VENDOR = VENDOR_GENERIC)) or (VENDOR = VENDOR_XILINX)) + assert ((VENDOR = VENDOR_ALTERA) or (SIMULATION and (VENDOR = VENDOR_GENERIC)) or (VENDOR = VENDOR_XILINX)) report "PoC.io.ddrio.out is not implemented for given DEVICE." severity FAILURE; diff --git a/src/io/io.pkg.vhdl b/src/io/io.pkg.vhdl index 548e131b0..a76510b84 100644 --- a/src/io/io.pkg.vhdl +++ b/src/io/io.pkg.vhdl @@ -209,24 +209,23 @@ package io is -- Component Declarations --------------------------------------------------------------------- component io_FanControl - generic ( - CLOCK_FREQ_MHZ : real + generic( + CLOCK_FREQ : FREQ; + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; + ENABLE_TACHO : boolean := FALSE ); - port ( - Clock : in std_logic; - Reset : in std_logic; - - Fan_PWM : out std_logic; - Fan_Tacho : in std_logic; - + port( + Clock : in std_logic; + Reset : in std_logic; + Fan_PWM : out std_logic; + Fan_Tacho : in std_logic := 'X'; TachoFrequency : out std_logic_vector(15 downto 0) ); - end component; + end component io_FanControl; end package; package body io is - function get_i_vector(vec : T_IO_TRISTATE_VECTOR) return std_logic_vector is variable temp : std_logic_vector(vec'range); begin diff --git a/src/io/io_FrequencyCounter.vhdl b/src/io/io_FrequencyCounter.vhdl index 3a44858dc..1ea70a6e2 100644 --- a/src/io/io_FrequencyCounter.vhdl +++ b/src/io/io_FrequencyCounter.vhdl @@ -53,7 +53,6 @@ end entity; architecture rtl of io_FrequencyCounter is constant TIMEBASECOUNTER_MAX : positive := TimingToCycles(TIMEBASE, CLOCK_FREQ); constant TIMEBASECOUNTER_BITS : positive := log2ceilnz(TIMEBASECOUNTER_MAX); - constant REQUENCYCOUNTER_MAX : positive := 2**RESOLUTION; constant FREQUENCYCOUNTER_BITS : positive := RESOLUTION; signal TimeBaseCounter_us : unsigned(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0'); diff --git a/src/io/io_GlitchFilter.vhdl b/src/io/io_GlitchFilter.vhdl index 98d20a259..7479f08aa 100644 --- a/src/io/io_GlitchFilter.vhdl +++ b/src/io/io_GlitchFilter.vhdl @@ -49,22 +49,22 @@ end entity; architecture rtl of io_GlitchFilter is -- Timing table ID - constant TTID_HIGH_SPIKE : natural := 0; - constant TTID_LOW_SPIKE : natural := 1; + constant TTID_HIGH_SPIKE : natural := 0; + constant TTID_LOW_SPIKE : natural := 1; -- Timing table - constant TIMING_TABLE : natural_vector := ( - TTID_HIGH_SPIKE => HIGH_SPIKE_SUPPRESSION_CYCLES, - TTID_LOW_SPIKE => LOW_SPIKE_SUPPRESSION_CYCLES + constant TIMING_TABLE : natural_vector := ( + TTID_HIGH_SPIKE => HIGH_SPIKE_SUPPRESSION_CYCLES, + TTID_LOW_SPIKE => LOW_SPIKE_SUPPRESSION_CYCLES ); - signal State : std_logic := '0'; - signal NextState : std_logic; + signal State : std_logic := '0'; + signal NextState : std_logic; - signal TC_en : std_logic; - signal TC_Load : std_logic; - signal TC_Slot : natural; - signal TC_Timeout : std_logic; + signal TC_en : std_logic; + signal TC_Load : std_logic; + signal TC_Slot : natural; + signal TC_Timeout : std_logic; begin assert FALSE diff --git a/src/io/io_TimingCounter.vhdl b/src/io/io_TimingCounter.vhdl index 1bd0b6674..3ac36b7d1 100644 --- a/src/io/io_TimingCounter.vhdl +++ b/src/io/io_TimingCounter.vhdl @@ -32,7 +32,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.project_configuration.all; +use work.config.all; use work.utils.all; @@ -54,10 +54,10 @@ architecture rtl of io_TimingCounter is function transform(vec : natural_vector) return integer_vector is variable Result : integer_vector(vec'range); begin - assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE; + assert not POC_VERBOSE report "TIMING_TABLE (transformed):" severity NOTE; for i in vec'range loop Result(i) := vec(i) - 1; - assert (not MY_VERBOSE) report " " & integer'image(i) & " - " & INTEGER'image(Result(i)) severity NOTE; + assert not POC_VERBOSE report " " & integer'image(i) & " - " & INTEGER'image(Result(i)) severity NOTE; end loop; return Result; end function; diff --git a/src/io/uart/uart.pkg.vhdl b/src/io/uart/uart.pkg.vhdl index 7fb7f471e..4ec0df69c 100644 --- a/src/io/uart/uart.pkg.vhdl +++ b/src/io/uart/uart.pkg.vhdl @@ -165,9 +165,9 @@ package uart is end component uart_FIFO; -- USB-UART - component ft245_uart is + component uart_FT245 is generic ( - CLK_FREQ : positive + CLOCK_FREQUENCY : positive ); port ( -- common signals diff --git a/src/io/uart/uart_FT245.vhdl b/src/io/uart/uart_FT245.vhdl index 1b1052b35..a9c8d9f06 100644 --- a/src/io/uart/uart_FT245.vhdl +++ b/src/io/uart/uart_FT245.vhdl @@ -33,7 +33,7 @@ use IEEE.std_logic_1164.all; entity uart_FT245 is generic ( - CLOCK_FREQ : positive -- XXX: use FREQ + CLOCK_FREQUENCY : positive -- XXX: use FREQ ); port ( -- common signals @@ -41,21 +41,21 @@ entity uart_FT245 is Reset : in std_logic; -- send data - snd_ready : out std_logic; -- XXX: this should fit the FIFO interface - snd_strobe : in std_logic; - snd_data : in std_logic_vector(7 downto 0); + TX_Put : in std_logic; + TX_Data : in std_logic_vector(7 downto 0); + TX_Full : out std_logic; -- receive data - rec_strobe : out std_logic; - rec_data : out std_logic_vector(7 downto 0); + RX_Valid : out std_logic; + RX_Data : out std_logic_vector(7 downto 0); -- connection to ft245 - ft245_data : inout std_logic_vector(7 downto 0); - ft245_rdn : out std_logic; - ft245_wrn : out std_logic; - ft245_rxfn : in std_logic; - ft245_txen : in std_logic; - ft245_pwrenn : in std_logic + FT245_PowerEnable_n : in std_logic; + FT245_Read_n : out std_logic; + FT245_Write_n : out std_logic; + FT245_Data : inout std_logic_vector(7 downto 0); + FT245_RXF_n : in std_logic; + FT245_TXE_n : in std_logic ); end entity; @@ -68,7 +68,7 @@ use work.utils.all; architecture rtl of uart_FT245 is -- clock frequency (MHz) - constant CLK_FREQ_MHZ : integer := CLOCK_FREQ / 1000000; + constant CLK_FREQ_MHZ : integer := CLOCK_FREQUENCY / 1000000; -- FT245 communication delay cycles (minimum delay is 50 ns = 1/20 us) constant DELAY_CYCLES : integer := CLK_FREQ_MHZ / 20; @@ -122,16 +122,16 @@ begin ff_txe <= '1'; else -- Wait for Initilization to Complete - ff_susp <= ft245_pwrenn; + ff_susp <= FT245_PowerEnable_n; -- Now forward Fill Signals - ff_rxf <= ft245_rxfn; - ff_txe <= ft245_txen; + ff_rxf <= FT245_RXF_n; + ff_txe <= FT245_TXE_n; end if; end if; end process; - process(fsm_state, snd_strobe, reg_delay, ff_susp, ff_rxf, ff_txe) + process(fsm_state, TX_Put, reg_delay, ff_susp, ff_rxf, ff_txe) begin fsm_nextstate <= fsm_state; ctrl_ld_rec <= '0'; @@ -146,7 +146,7 @@ begin if ff_rxf = '0' then -- receive data fsm_nextstate <= RD1; - elsif ff_txe = '0' and snd_strobe = '1' then + elsif ff_txe = '0' and TX_Put = '1' then -- ok, send... fsm_nextstate <= WR1; end if; @@ -236,8 +236,8 @@ begin end if; -- data to send - if snd_strobe = '1' then - reg_data_snd <= snd_data; + if TX_Put = '1' then + reg_data_snd <= TX_Data; end if; end if; @@ -245,14 +245,14 @@ begin ---------------------------------------------- -- tristate driver and output assignments - ft245_data <= reg_data_snd when reg_dto_b = '0' else (others => 'Z'); - data_in <= ft245_data; + FT245_Data <= reg_data_snd when reg_dto_b = '0' else (others => 'Z'); + data_in <= FT245_Data; - ft245_rdn <= reg_rd_b; - ft245_wrn <= reg_wr_b; + FT245_Read_n <= reg_rd_b; + FT245_Write_n <= reg_wr_b; - rec_data <= reg_data_rec; - rec_strobe <= reg_ld_rec; - snd_ready <= ff_rxf and not ff_txe and not ff_susp when fsm_state = IDLE else '0'; + RX_Data <= reg_data_rec; + RX_Valid <= reg_ld_rec; + TX_Full <= not ff_rxf and not ff_txe and not ff_susp when fsm_state = IDLE else '0'; end architecture; diff --git a/src/mem/mem.pkg.vhdl b/src/mem/mem.pkg.vhdl index e548e1369..41b3f6bbd 100644 --- a/src/mem/mem.pkg.vhdl +++ b/src/mem/mem.pkg.vhdl @@ -118,7 +118,7 @@ package body mem is DATA_BITS : positive ) return T_SLVV is variable memory : T_SLM(WORDS - 1 downto 0, DATA_BITS - 1 downto 0); - variable empty : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := (others => (others => ite(SIMULATION, 'U', '0'))); + constant empty : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := (others => (others => ite(SIMULATION, 'U', '0'))); begin if str_length(FilePath) = 0 then -- shortcut required by Vivado diff --git a/src/mem/ocram/ocram.pkg.vhdl b/src/mem/ocram/ocram.pkg.vhdl index 97a9d314d..95aba6d26 100644 --- a/src/mem/ocram/ocram.pkg.vhdl +++ b/src/mem/ocram/ocram.pkg.vhdl @@ -78,9 +78,9 @@ package ocram is -- Simple-Dual-Port component ocram_SimpleDualPort generic( + RAM_TYPE : T_RAM_TYPE := RAM_TYPE_AUTO; ADDRESS_BITS : positive; DATA_BITS : positive; - RAM_TYPE : T_RAM_TYPE := RAM_TYPE_AUTO; FILENAME : string := "" ); port( @@ -99,23 +99,25 @@ package ocram is -- Enhanced-Simple-Dual-Port component ocram_EnhancedSimpleDualPort - generic ( + generic( ADDRESS_BITS : positive; DATA_BITS : positive; - FILENAME : string := "" + FILENAME : string := "" ); - port ( + port( PortA_Clock : in std_logic; - PortB_Clock : in std_logic; PortA_ClockEnable : in std_logic; - PortB_ClockEnable : in std_logic; PortA_WriteEnable : in std_logic; PortA_Address : in unsigned(ADDRESS_BITS-1 downto 0); - PortB_Address : in unsigned(ADDRESS_BITS-1 downto 0); PortA_DataIn : in std_logic_vector(DATA_BITS-1 downto 0); PortA_DataOut : out std_logic_vector(DATA_BITS-1 downto 0); - PortB_DataOut : out std_logic_vector(DATA_BITS-1 downto 0)); - end component; + + PortB_Clock : in std_logic; + PortB_ClockEnable : in std_logic; + PortB_Address : in unsigned(ADDRESS_BITS-1 downto 0); + PortB_DataOut : out std_logic_vector(DATA_BITS-1 downto 0) + ); + end component ocram_EnhancedSimpleDualPort; -- True-Dual-Port component ocram_TrueDualPort diff --git a/src/mem/ocrom/ocrom.pkg.vhdl b/src/mem/ocrom/ocrom.pkg.vhdl index 7d7bdadb1..a5e566709 100644 --- a/src/mem/ocrom/ocrom.pkg.vhdl +++ b/src/mem/ocrom/ocrom.pkg.vhdl @@ -51,21 +51,22 @@ package ocrom is end component; -- Dual-Port - component ocrom_DualPort is - generic ( - ADDRESS_BITS : positive; + component ocrom_DualPort + generic( + ADDRESS_BITS : positive; DATA_BITS : positive; - FILENAME : string := "" + FILENAME : string := "" ); - port ( - PortA_Clock : in std_logic; - PortB_Clock : in std_logic; - PortA_ClockEnable : in std_logic; - PortB_ClockEnable : in std_logic; - PortA_Address : in unsigned(ADDRESS_BITS-1 downto 0); - PortB_Address : in unsigned(ADDRESS_BITS-1 downto 0); - PortA_DataOut : out std_logic_vector(DATA_BITS-1 downto 0); - PortB_DataOut : out std_logic_vector(DATA_BITS-1 downto 0) + port( + PortA_Clock : in std_logic; + PortA_ClockEnable : in std_logic; + PortA_Address : in unsigned(ADDRESS_BITS-1 downto 0); + PortA_DataOut : out std_logic_vector(DATA_BITS-1 downto 0); + + PortB_Clock : in std_logic; + PortB_ClockEnable : in std_logic; + PortB_Address : in unsigned(ADDRESS_BITS-1 downto 0); + PortB_DataOut : out std_logic_vector(DATA_BITS-1 downto 0) ); - end component; + end component ocrom_DualPort; end package; diff --git a/src/net/arp/arp_BroadCast_Receiver.vhdl b/src/net/arp/arp_BroadCast_Receiver.vhdl index 9cf07679f..a65950f0f 100644 --- a/src/net/arp/arp_BroadCast_Receiver.vhdl +++ b/src/net/arp/arp_BroadCast_Receiver.vhdl @@ -231,10 +231,10 @@ begin RX_Ack <= '1'; if (Is_EOF = '0') then - if ((ALLOWED_PROTOCOL_IPV4 = TRUE) and (RX_Data = x"08")) then + if (ALLOWED_PROTOCOL_IPV4 and (RX_Data = x"08")) then IsIPv4_set <= '1'; NextState <= ST_RECEIVE_PROTOCOL_type_1; - elsif ((ALLOWED_PROTOCOL_IPV6 = TRUE) and (RX_Data = x"86")) then + elsif (ALLOWED_PROTOCOL_IPV6 and (RX_Data = x"86")) then IsIPv6_set <= '1'; NextState <= ST_RECEIVE_PROTOCOL_type_1; else diff --git a/tb/arith/SquareRoot/arith_SquareRoot_TestHarness.vhdl b/tb/arith/SquareRoot/arith_SquareRoot_TestHarness.vhdl index 159a024cb..0baa33412 100644 --- a/tb/arith/SquareRoot/arith_SquareRoot_TestHarness.vhdl +++ b/tb/arith/SquareRoot/arith_SquareRoot_TestHarness.vhdl @@ -84,7 +84,7 @@ begin port map ( Reset => Reset, Clock => Clock, - Operand => arg, + Radicand => arg, Start => start, Result => sqrt, Ready => rdy From cbaf0fddd83b51996d303da75b13680c635f9c53 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 17:00:10 +0200 Subject: [PATCH 11/18] Fixed more warnings reported by Sigasi. --- src/net/arp/arp_BroadCast_Receiver.vhdl | 3 -- src/net/arp/arp_BroadCast_Requester.vhdl | 2 +- src/net/arp/arp_Cache.vhdl | 51 +++++++------------ src/net/arp/arp_UniCast_Receiver.vhdl | 10 +--- src/net/arp/arp_Wrapper.vhdl | 4 +- src/sync/sync.pkg.vhdl | 23 +++++---- src/xil/reconfig/reconfig_ICAP_FSM.vhdl | 2 +- src/xil/xil_Reconfigurator.vhdl | 17 +++---- .../Adder_Wide/arith_Adder_Wide_Simple.vhdl | 3 +- .../Counter_BCD/arith_Counter_BCD_Simple.vhdl | 4 +- tb/arith/TRNG/arith_TRNG_Simple.vhdl | 14 ++--- 11 files changed, 55 insertions(+), 78 deletions(-) diff --git a/src/net/arp/arp_BroadCast_Receiver.vhdl b/src/net/arp/arp_BroadCast_Receiver.vhdl index a65950f0f..99fd77294 100644 --- a/src/net/arp/arp_BroadCast_Receiver.vhdl +++ b/src/net/arp/arp_BroadCast_Receiver.vhdl @@ -98,9 +98,6 @@ architecture rtl of arp_BroadCast_Receiver is constant PROTOCOL_IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes constant PROTOCOL_ADDRESS_LENGTH : positive := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes - subtype T_HARDWARE_ADDRESS_INDEX is natural range 0 to HARDWARE_ADDRESS_LENGTH - 1; - subtype T_PROTOCOL_ADDRESS_INDEX is natural range 0 to PROTOCOL_ADDRESS_LENGTH - 1; - signal IsIPv4_set : std_logic; signal IsIPv4_r : std_logic := '0'; signal IsIPv6_set : std_logic; diff --git a/src/net/arp/arp_BroadCast_Requester.vhdl b/src/net/arp/arp_BroadCast_Requester.vhdl index 25be37fe8..23fdb0fa7 100644 --- a/src/net/arp/arp_BroadCast_Requester.vhdl +++ b/src/net/arp/arp_BroadCast_Requester.vhdl @@ -118,7 +118,7 @@ begin process(State, SendRequest, IsIPv4_l, IsIPv6_l, - TX_Ack, TX_Meta_DestMACAddress_rst, TX_Meta_DestMACAddress_nxt, + TX_Ack, SenderMACAddress_Data, SenderIPv4Address_Data, TargetMACAddress_Data, TargetIPv4Address_Data, Reader_Counter_us) begin diff --git a/src/net/arp/arp_Cache.vhdl b/src/net/arp/arp_Cache.vhdl index e093b7046..eb7bbff81 100644 --- a/src/net/arp/arp_Cache.vhdl +++ b/src/net/arp/arp_Cache.vhdl @@ -114,7 +114,7 @@ architecture rtl of arp_Cache is return result; end function; - constant INITIAL_TAGS : T_SLM := to_TagData(INITIAL_CACHE_CONTENT); + constant INITIAL_TAGS : T_SLM := to_TagData(INITIAL_CACHE_CONTENT); constant INITIAL_DATALINES : T_SLVV_8 := to_CacheMemory(INITIAL_CACHE_CONTENT); @@ -122,10 +122,10 @@ architecture rtl of arp_Cache is type T_FSMREPLACE_STATE is (ST_IDLE, ST_REPLACE); - signal FSMReplace_State : T_FSMREPLACE_STATE := ST_IDLE; - signal FSMReplace_NextState : T_FSMREPLACE_STATE; + signal FSMReplace_State : T_FSMREPLACE_STATE := ST_IDLE; + signal FSMReplace_NextState : T_FSMREPLACE_STATE; - signal Insert : std_logic; + signal Insert : std_logic; signal TU_NewTag_rst : std_logic; signal TU_NewTag_nxt : std_logic; @@ -133,40 +133,32 @@ architecture rtl of arp_Cache is signal NewCacheLine_Data : T_SLV_8; - signal TU_Tag_rst : std_logic; - signal TU_Tag_nxt : std_logic; + signal TU_Tag_rst : std_logic; + signal TU_Tag_nxt : std_logic; signal TU_Tag_Data : T_SLV_8; - signal CacheHit : std_logic; + signal CacheHit : std_logic; signal CacheMiss : std_logic; - signal TU_Index : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Index_d : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); --- signal TU_Index_us : UNSIGNED(CACHEMEMORY_INDEX_BITS - 1 downto 0); - + signal TU_Index : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); signal TU_NewIndex : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Replaced : std_logic; signal TU_TagHit : std_logic; - signal TU_TagMiss : std_logic; + signal TU_TagMiss : std_logic; constant TICKCOUNTER_RES : T_TIME := 10.0e-3; constant TICKCOUNTER_MAX : positive := TimingToCycles(TICKCOUNTER_RES, CLOCK_FREQ); - constant TICKCOUNTER_BITS : positive := log2ceilnz(TICKCOUNTER_MAX); + constant TICKCOUNTER_BITS : positive := log2ceilnz(TICKCOUNTER_MAX); signal TickCounter_s : signed(TICKCOUNTER_BITS downto 0) := to_signed(TICKCOUNTER_MAX, TICKCOUNTER_BITS + 1); - signal Tick : std_logic; - - signal Exp_Expired : std_logic; - signal Exp_KeyOut : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal Tick : std_logic; - signal DataChunkIndex_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal DataChunkIndex_l_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal NewDataChunkIndex_en : std_logic; - signal NewDataChunkIndex_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal NewDataChunkIndex_max_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal CacheMemory_we : std_logic; - signal CacheMemory : T_SLVV_8((CACHE_LINES * T_NET_MAC_ADDRESS'length) - 1 downto 0) := INITIAL_DATALINES; - signal Memory_ReadWrite : std_logic; + signal DataChunkIndex_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal DataChunkIndex_l_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal NewDataChunkIndex_en : std_logic; + signal NewDataChunkIndex_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal NewDataChunkIndex_max_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal CacheMemory_we : std_logic; + signal CacheMemory : T_SLVV_8((CACHE_LINES * T_NET_MAC_ADDRESS'length) - 1 downto 0) := INITIAL_DATALINES; begin process(Clock) @@ -180,7 +172,7 @@ begin end if; end process; - process(FSMReplace_State, Command, TU_Replaced, TU_NewTag_rst, TU_NewTag_nxt, NewDataChunkIndex_us, NewDataChunkIndex_max_us) + process(FSMReplace_State, Command, TU_NewTag_rst, TU_NewTag_nxt, NewDataChunkIndex_us, NewDataChunkIndex_max_us) begin FSMReplace_NextState <= FSMReplace_State; @@ -215,8 +207,6 @@ begin FSMReplace_NextState <= ST_REPLACE; - when others => - null; end case; when ST_REPLACE => @@ -368,9 +358,6 @@ begin end if; end process; - -- Cache Memory - port 1 - Memory_ReadWrite <= ReadWrite; - process(Clock) begin if rising_edge(Clock) then diff --git a/src/net/arp/arp_UniCast_Receiver.vhdl b/src/net/arp/arp_UniCast_Receiver.vhdl index 9fb67faf2..32f5dd36c 100644 --- a/src/net/arp/arp_UniCast_Receiver.vhdl +++ b/src/net/arp/arp_UniCast_Receiver.vhdl @@ -75,9 +75,6 @@ end entity; architecture rtl of arp_UniCast_Receiver is attribute FSM_ENCODING : string; - subtype T_MAC_BYTEINDEX is natural range 0 to 5; - subtype T_IP_BYTEINDEX is natural range 0 to 3; - type T_STATE is ( ST_IDLE, ST_RECEIVE_HARDWARE_TYPE_1, @@ -103,9 +100,6 @@ architecture rtl of arp_UniCast_Receiver is constant PROTOCOL_IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes constant PROTOCOL_ADDRESS_LENGTH : positive := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes - subtype T_HARDWARE_ADDRESS_INDEX is natural range 0 to HARDWARE_ADDRESS_LENGTH - 1; - subtype T_PROTOCOL_ADDRESS_INDEX is natural range 0 to PROTOCOL_ADDRESS_LENGTH - 1; - signal IsIPv4_set : std_logic; signal IsIPv4_r : std_logic := '0'; signal IsIPv6_set : std_logic; @@ -244,10 +238,10 @@ begin RX_Ack <= '1'; if (Is_EOF = '0') then - if ((ALLOWED_PROTOCOL_IPV4 = TRUE) and (RX_Data = x"08")) then + if (ALLOWED_PROTOCOL_IPV4 and (RX_Data = x"08")) then IsIPv4_set <= '1'; NextState <= ST_RECEIVE_PROTOCOL_TYPE_1; - elsif ((ALLOWED_PROTOCOL_IPV6 = TRUE) and (RX_Data = x"86")) then + elsif (ALLOWED_PROTOCOL_IPV6 and (RX_Data = x"86")) then IsIPv6_set <= '1'; NextState <= ST_RECEIVE_PROTOCOL_TYPE_1; else diff --git a/src/net/arp/arp_Wrapper.vhdl b/src/net/arp/arp_Wrapper.vhdl index 8faa24421..d064854a8 100644 --- a/src/net/arp/arp_Wrapper.vhdl +++ b/src/net/arp/arp_Wrapper.vhdl @@ -519,9 +519,9 @@ begin process(FSMCache_State, IPCache_Lookup, IPCache_IPv4Address_Data, IPCache_MACAddress_rst, IPCache_MACAddress_nxt, MACSeq2_SenderMACAddress_Data, IPSeq2_SenderIPv4Address_Data, ARPReq_Timeout, - UCRcv_Error, UCRcv_ResponseReceived, UCRcv_SenderIPv4Address_Data, UCRcv_SenderMACAddress_Data, UCRcv_TargetIPv4Address_Data, UCRcv_TargetMACAddress_Data, + UCRcv_Error, UCRcv_ResponseReceived, UCRcv_SenderIPv4Address_Data, UCRcv_SenderMACAddress_Data, ARPCache_Status, ARPCache_CacheResult, ARPCache_IPv4Address_rst, ARPCache_IPv4Address_nxt, ARPCache_MACAddress_Data, ARPCache_NewMACAddress_nxt, ARPCache_NewIPv4Address_nxt, - BCReq_Address_rst, BCReq_SenderMACAddress_nxt, BCReq_SenderIPv4Address_nxt, BCReq_TargetMACAddress_nxt, BCReq_TargetIPv4Address_nxt, BCReq_Complete) + BCReq_Address_rst, BCReq_SenderMACAddress_nxt, BCReq_SenderIPv4Address_nxt, BCReq_TargetIPv4Address_nxt, BCReq_Complete) begin FSMCache_NextState <= FSMCache_State; diff --git a/src/sync/sync.pkg.vhdl b/src/sync/sync.pkg.vhdl index 26f7bc978..e0637d9b9 100644 --- a/src/sync/sync.pkg.vhdl +++ b/src/sync/sync.pkg.vhdl @@ -106,17 +106,18 @@ package sync is ); end component; - component sync_Reset_Xilinx is - generic ( - SYNC_DEPTH : T_MISC_SYNC_DEPTH := T_MISC_SYNC_DEPTH'low -- generate SYNC_DEPTH many stages, at least 2 - ); - port ( - Clock : in std_logic; -- output clock domain - Input : in std_logic; -- @async: reset input - D : in std_logic := '0'; - Output : out std_logic -- @Clock: reset output - ); - end component; + component sync_Reset_Xilinx + generic( + REGISTER_OUTPUT : boolean := true; + SYNC_DEPTH : T_MISC_SYNC_DEPTH := T_MISC_SYNC_DEPTH'low + ); + port( + Clock : in std_logic; + Input : in std_logic; + D : in std_logic := '0'; + Output : out std_logic + ); + end component sync_Reset_Xilinx; component sync_Pulse is generic ( diff --git a/src/xil/reconfig/reconfig_ICAP_FSM.vhdl b/src/xil/reconfig/reconfig_ICAP_FSM.vhdl index 1865bb3fc..40a9536ba 100644 --- a/src/xil/reconfig/reconfig_ICAP_FSM.vhdl +++ b/src/xil/reconfig/reconfig_ICAP_FSM.vhdl @@ -135,7 +135,7 @@ begin -- combinatorial state machine cur_state <= nxt_state when rising_edge(Clock); - combi : process (Reset, nxt_state, cur_state, in_data, in_data_valid, in_data_valid_re, + combi : process (Reset, cur_state, in_data, in_data_valid, in_data_valid_re, sync_state, sync_state_flag, out_data_full, readback_cnt, pr_reset) begin -- default assignments nxt_state <= cur_state; diff --git a/src/xil/xil_Reconfigurator.vhdl b/src/xil/xil_Reconfigurator.vhdl index e6e158af8..f3c5e4510 100644 --- a/src/xil/xil_Reconfigurator.vhdl +++ b/src/xil/xil_Reconfigurator.vhdl @@ -46,24 +46,24 @@ use work.xil.all; entity xil_Reconfigurator is generic ( - DEBUG : boolean := FALSE; -- - CLOCK_FREQ : FREQ := 100 MHz; -- + DEBUG : boolean := FALSE; -- + CLOCK_FREQUENCY : FREQ := 100 MHz; -- CONFIG_ROM : in T_XIL_DRP_CONFIG_ROM := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY) -- ); port ( - Clock : in std_logic; - Reset : in std_logic; + Clock : in std_logic; + Reset : in std_logic; Reconfig : in std_logic; -- ReconfigDone : out std_logic; -- ConfigSelect : in std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); -- DRP_Enable : out std_logic; -- - DRP_Address : out T_XIL_DRP_ADDRESS; -- - DRP_WriteEnable : out std_logic; -- + DRP_Address : out T_XIL_DRP_ADDRESS; -- + DRP_WriteEnable : out std_logic; -- DRP_DataIn : in T_XIL_DRP_DATA; -- - DRP_DataOut : out T_XIL_DRP_DATA; -- - DRP_Ack : in std_logic -- + DRP_DataOut : out T_XIL_DRP_DATA; -- + DRP_Ack : in std_logic -- ); end entity; @@ -71,7 +71,6 @@ end entity; architecture rtl of xil_Reconfigurator is attribute KEEP : boolean; attribute FSM_ENCODING : string; - attribute signal_ENCODING : string; type T_STATE is ( ST_IDLE, diff --git a/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl b/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl index 575539652..f2844cbce 100644 --- a/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl +++ b/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl @@ -42,7 +42,6 @@ use work.arith_Adder_Wide_TestController_pkg.all; architecture Simple of arith_Adder_Wide_TestController is signal TestDone : integer_barrier := 1; constant TCID : AlertLogIDType := NewID("Adder_WideTest"); - constant TPERIOD_CLOCK : time := 10 ns; begin @@ -73,7 +72,7 @@ begin CheckerProc: process constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID); - variable ai, bi : integer; + variable expected : natural; variable actual_sum : unsigned(9 downto 0); begin diff --git a/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl b/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl index 090f84167..0a5d165f6 100644 --- a/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl +++ b/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl @@ -40,9 +40,9 @@ use PoC.physical.all; architecture Simple of arith_Counter_BCD_TestController is constant TCID : AlertLogIDType := NewID("CntBCDTest"); - signal TestDone : integer_barrier := 1; - signal Expected : T_BCD_VECTOR(DIGITS - 1 downto 0); + signal TestDone : integer_barrier := 1; + begin ControlProc: process diff --git a/tb/arith/TRNG/arith_TRNG_Simple.vhdl b/tb/arith/TRNG/arith_TRNG_Simple.vhdl index ae741f3f3..93fed2f4c 100644 --- a/tb/arith/TRNG/arith_TRNG_Simple.vhdl +++ b/tb/arith/TRNG/arith_TRNG_Simple.vhdl @@ -68,7 +68,7 @@ begin CheckerProc: process constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID); constant NUM_SAMPLES : natural := 100; - + variable prev_rnd : std_logic_vector(rnd'range); variable changes : natural := 0; variable has_zeros : boolean := false; @@ -81,11 +81,11 @@ begin -- are not accurately modeled in simulation. This test verifies basic functionality -- but cannot validate true randomness. True TRNG validation must be done on -- actual hardware using tools like dieharder. - + -- Verify the component produces output prev_rnd := rnd; WaitForClock(Clock); - + -- Sample multiple times to check if any variation occurs for i in 1 to NUM_SAMPLES loop if rnd /= prev_rnd then @@ -104,21 +104,21 @@ begin -- Basic sanity checks that are simulation-friendly -- Note: In simulation, TRNG may produce constant or deterministic output - Log(ProcID, "TRNG changes observed: " & integer'image(changes) & + Log(ProcID, "TRNG changes observed: " & integer'image(changes) & " out of " & integer'image(NUM_SAMPLES) & " samples", INFO); - + -- Note: TRNG output will be 'X' or 'U' in simulation because it relies on -- physical randomness sources (oscillator jitter, metastability) that cannot -- be accurately simulated. This is expected behavior. Log(ProcID, "WARNING: TRNG output is undefined ('X'/'U') in simulation."); Log(ProcID, "This is expected - TRNG relies on physical phenomena."); Log(ProcID, "Verify randomness on target hardware using dieharder or similar tools."); - + -- Just verify the component doesn't crash for i in 1 to 10 loop WaitForClock(Clock); end loop; - + -- Mark test as passed since simulation limitations are expected AffirmIf(ProcID, true, "TRNG component instantiated successfully"); From 27cb0551c9c9b24c24a18299abc8235df31951c8 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 17:04:20 +0200 Subject: [PATCH 12/18] Fixes after removinbg unused code. --- src/bus/axi4/axi4_DeMux.vhdl | 2 +- src/bus/axi4/axi4_Mux.vhdl | 2 +- src/net/arp/arp_Cache.vhdl | 50 ++++++++++++++++++------------------ 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/bus/axi4/axi4_DeMux.vhdl b/src/bus/axi4/axi4_DeMux.vhdl index b5a9da175..b44595c92 100644 --- a/src/bus/axi4/axi4_DeMux.vhdl +++ b/src/bus/axi4/axi4_DeMux.vhdl @@ -286,7 +286,7 @@ begin begin NextState <= State; - In_S2M_write <= Initialize_AXI4_Bus_S2M(In_M2S.AWAddr'length, In_S2M.RData'length, In_S2M.RUser'length, In_S2M.BID'length, '0'); + In_S2M_write <= Initialize_AXI4_Bus_S2M(In_S2M.RData'length, In_S2M.RUser'length, In_S2M.BID'length, '0'); Out_M2S_write <= (Out_M2S'range => In_M2S_write); for i in 0 to PORTS -1 loop diff --git a/src/bus/axi4/axi4_Mux.vhdl b/src/bus/axi4/axi4_Mux.vhdl index 353270d95..1f7fd57ea 100644 --- a/src/bus/axi4/axi4_Mux.vhdl +++ b/src/bus/axi4/axi4_Mux.vhdl @@ -202,7 +202,7 @@ begin begin NextState <= State; - In_S2M_write <= (In_S2M'range => Initialize_AXI4_Bus_S2M(Out_M2S.AWAddr'length, Out_S2M.RData'length, Out_S2M.RUser'length, In_S2M(In_S2M'low).BID'length, '0')); + In_S2M_write <= (In_S2M'range => Initialize_AXI4_Bus_S2M(Out_S2M.RData'length, Out_S2M.RUser'length, In_S2M(In_S2M'low).BID'length, '0')); Out_M2S_write <= Initialize_AXI4_Bus_M2S(Out_M2S.AWAddr'length, Out_M2S.WData'length, Out_M2S.WUser'length, Out_M2S.AWID'length, '0'); Arbitrate <= '0'; diff --git a/src/net/arp/arp_Cache.vhdl b/src/net/arp/arp_Cache.vhdl index eb7bbff81..4f56c603a 100644 --- a/src/net/arp/arp_Cache.vhdl +++ b/src/net/arp/arp_Cache.vhdl @@ -201,8 +201,8 @@ begin Insert <= '1'; CacheMemory_we <= '1'; - NewMACAddress_rst <= '0'; - NewMACAddress_nxt <= '1'; + NewMACAddress_rst <= '0'; + NewMACAddress_nxt <= '1'; NewDataChunkIndex_en <= '1'; FSMReplace_NextState <= ST_REPLACE; @@ -213,7 +213,7 @@ begin Status <= NET_ARP_ARPCACHE_STATUS_UPDATING; CacheMemory_we <= '1'; - NewMACAddress_nxt <= '1'; + NewMACAddress_nxt <= '1'; NewDataChunkIndex_en <= '1'; if (NewDataChunkIndex_us = NewDataChunkIndex_max_us) then @@ -238,36 +238,36 @@ begin TU: entity work.cache_TagUnit_Sequential generic map ( REPLACEMENT_POLICY => REPLACEMENT_POLICY, - CACHE_LINES => CACHE_LINES, - ASSOCIATIVITY => CACHE_LINES, + CACHE_LINES => CACHE_LINES, + ASSOCIATIVITY => CACHE_LINES, TAG_BITS => TAG_BITS, CHUNK_BITS => TAGCHUNK_BITS, TAG_BYTE_ORDER => TAG_BYTE_ORDER, - USE_INITIAL_TAGS => TRUE, + USE_INITIAL_TAGS => TRUE, INITIAL_TAGS => INITIAL_TAGS ) port map ( - Clock => Clock, - Reset => Reset, + Clock => Clock, + Reset => Reset, - Replace => Insert, - Replaced => TU_Replaced, + Replace => Insert, + Replaced => open, Replace_NewTag_rst => TU_NewTag_rst, Replace_NewTag_rev => open, Replace_NewTag_nxt => TU_NewTag_nxt, - Replace_NewTag_Data => NewTag_Data, + Replace_NewTag_Data => NewTag_Data, Replace_NewIndex => TU_NewIndex, - Request => Lookup, - Request_ReadWrite => '0', + Request => Lookup, + Request_ReadWrite => '0', Request_Invalidate => '0',--Invalidate, - Request_Tag_rst => TU_Tag_rst, - Request_Tag_rev => open, - Request_Tag_nxt => TU_Tag_nxt, + Request_Tag_rst => TU_Tag_rst, + Request_Tag_rev => open, + Request_Tag_nxt => TU_Tag_nxt, Request_Tag_Data => TU_Tag_Data, - Request_Index => TU_Index, + Request_Index => TU_Index, Request_TagHit => TU_TagHit, - Request_TagMiss => TU_TagMiss + Request_TagMiss => TU_TagMiss ); -- expiration time tick generator @@ -287,22 +287,22 @@ begin -- Exp: entity work.list_Expire Exp: entity work.list_Expire generic map ( - CLOCK_CYCLE_TICKS => 65536, - EXPIRATION_TIME_TICKS => 8192, + CLOCK_CYCLE_TICKS => 65536, + EXPIRATION_TIME_TICKS => 8192, ELEMENTS => CACHE_LINES, KEY_BITS => CACHEMEMORY_INDEX_BITS ) port map ( - Clock => Clock, - Reset => Reset, + Clock => Clock, + Reset => Reset, Tick => Tick, Insert => Insert, - KeyIn => TU_NewIndex, + KeyIn => TU_NewIndex, - Expired => Exp_Expired, - KeyOut => Exp_KeyOut + Expired => open, -- FIXME: why is it not used? + KeyOut => open ); From a7157a457f47d1eb6d3556141027e53ffb22921c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 17:32:25 +0200 Subject: [PATCH 13/18] Simplified GitLab-CI script. --- .gitlab-ci.yml | 345 ++++++++++++++----------------------------------- 1 file changed, 100 insertions(+), 245 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 79b609c1b..0395bbd08 100755 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,26 +1,14 @@ stages: - - prepare - - build_osvvm - - build_poc - - test - - documentation - - pages +# - prepare + - Build-OSVVM + - Build-PoC + - Simulate + - Documentation + - GitLabPages variables: GIT_SUBMODULE_STRATEGY: recursive - SIMULATOR_PAGES: "NVC" # simulator from which the results should be published on GitLab pages (GHDL, Riviera-PRO) - -Scripts: - stage: prepare - image: ${CI_REGISTRY}/docker-images/base-image:alpine - script: - - mv src/common/local_configuration.vhdl.template tb/common/local_configuration.vhdl # use CopyFile when its supporting renaming - - sed -i 's#\(constant\sLOCAL_PROJECT_DIR\s*:\s*string\s*:=\s*\)".*";#\1"'"$(pwd)"'";#' tb/common/local_configuration.vhdl - artifacts: - paths: - - tb/common/local_configuration.vhdl - expire_in: 1 hour - + SIMULATOR_PAGES: "nvc" # simulator from which the results should be published on GitLab pages (GHDL, Riviera-PRO) # -------------------- # ---- Templates ----- @@ -28,22 +16,22 @@ Scripts: .run: script: - | - if [ "$SIMULATOR" = "NVC" ]; then + if [[ "${SIMULATOR_TOOL}" == "NVC" ]]; then CreateAndChangeDirectory "temp/NVC" "Simulation working directory" # before_script and script are running in the same shell; therefore no need to change the directory nvc --do ../../regression.tcl else - exec-$SIMULATOR.sh -n --tcl-file=regression.tcl + exec-${SIMULATOR_TOOL}.sh -n --tcl-file=regression.tcl fi after_script: - mkdir -p temp/junit - - CopyFile "temp/$SIMULATOR/*/*.xml" "temp/junit" - - CopyFile "temp/$SIMULATOR/*/*.yml" "temp/junit" + - CopyFile temp/${SIMULATOR_TOOL}/*/*.xml "temp/junit" + - CopyFile temp/${SIMULATOR_TOOL}/*/*.yml "temp/junit" artifacts: paths: - - temp/$SIMULATOR + - temp/[GNR]* - temp/junit - - lib/osvvm/*_generated.vhd + - lib/osvvm/*_generated.vhd reports: junit: "temp/junit/*.xml" expire_in: 1 week @@ -52,47 +40,65 @@ Scripts: # --------------- # ---- GHDL ----- # --------------- -.GHDL: - parallel: - matrix: - - GHDL_BACKEND: ["llvm", "mcode"] - image: ${CI_REGISTRY}/docker-images/ghdl:${GHDL_BACKEND} +OSVVM-build: extends: - .run - variables: - SIMULATOR: "GHDL" - -GHDL_OSVVM_run: - stage: build_osvvm - extends: - - .GHDL - needs: - job: Scripts - artifacts: true + stage: Build-OSVVM + image: ${CI_REGISTRY}/docker-images/${IMAGE}:${VERSION} + parallel: + matrix: + - IMAGE: "rivierapro" + VERSION: "2024.10" + - IMAGE: "nvc" + VERSION: "latest" + - IMAGE: "ghdl" + VERSION: ["llvm", "mcode"] variables: REGRESSION_STEP: "osvvm" -GHDL_PoC_run: - stage: build_poc +PoC-build: extends: - - .GHDL + - .run + stage: Build-PoC + image: ${CI_REGISTRY}/docker-images/${IMAGE}:${VERSION} + parallel: + matrix: + - IMAGE: "rivierapro" + VERSION: "2024.10" + - IMAGE: "nvc" + VERSION: "latest" + - IMAGE: "ghdl" + VERSION: ["llvm", "mcode"] needs: - - job: Scripts - artifacts: true - - job: GHDL_OSVVM_run + - job: OSVVM-build artifacts: true + parallel: + matrix: + - IMAGE: $[[ matrix.IMAGE ]] + VERSION: $[[ matrix.VERSION ]] variables: REGRESSION_STEP: "poc" -.GHDL_OSVVM_sim: # step has to be added to regression.tcl - stage: test +.OSVVM-sim: # step has to be added to regression.tcl extends: - - .GHDL + - .run + stage: Simulate + image: ${CI_REGISTRY}/docker-images/${IMAGE}:${VERSION} + parallel: + matrix: + - IMAGE: "rivierapro" + VERSION: "2024.10" + - IMAGE: "nvc" + VERSION: "latest" + - IMAGE: "ghdl" + VERSION: ["llvm", "mcode"] needs: - - job: Scripts - artifacts: true - - job: GHDL_OSVVM_run + - job: OSVVM-build artifacts: true + parallel: + matrix: + - IMAGE: $[[ matrix.IMAGE ]] + VERSION: $[[ matrix.VERSION ]] only: - main - master @@ -100,174 +106,51 @@ GHDL_PoC_run: variables: REGRESSION_STEP: "osvvm_test" # todo: add this to regression.tcl -GHDL_PoC_sim: - stage: test - extends: - - .GHDL - needs: - - job: Scripts - artifacts: true - - job: GHDL_PoC_run - artifacts: true - allow_failure: true # todo: fix llvm error - variables: - REGRESSION_STEP: "test" - -# ------------------ -# ---- Riviera ----- -# ------------------ -.RIVIERA-PRO: - image: ${CI_REGISTRY}/docker-images/rivierapro:2024.10 +PoC-sim: extends: - .run - variables: - SIMULATOR: "Riviera-PRO" - -RIVIERA_OSVVM_run: - stage: build_osvvm - extends: - - .RIVIERA-PRO - needs: - job: Scripts - artifacts: true - variables: - REGRESSION_STEP: "osvvm" - -RIVIERA_PoC_run: - stage: build_poc - extends: - - .RIVIERA-PRO - needs: - - job: Scripts - artifacts: true - - job: RIVIERA_OSVVM_run - artifacts: true - variables: - REGRESSION_STEP: "poc" - -.RIVIERA_OSVVM_sim: - stage: test - extends: - - .RIVIERA-PRO + stage: Simulate + image: ${CI_REGISTRY}/docker-images/${IMAGE}:${VERSION} + parallel: + matrix: + - IMAGE: "rivierapro" + VERSION: "2024.10" + - IMAGE: "nvc" + VERSION: "latest" + - IMAGE: "ghdl" + VERSION: ["llvm", "mcode"] needs: - - job: Scripts - artifacts: true - - job: RIVIERA_OSVVM_run + - job: PoC-build artifacts: true - - job: RIVIERA_PoC_run # avoid license blocking - artifacts: true - only: - - main - - master - - dev + parallel: + matrix: + - IMAGE: $[[ matrix.IMAGE ]] + VERSION: $[[ matrix.VERSION ]] allow_failure: true - variables: - REGRESSION_STEP: "osvvm_test" - -RIVIERA_PoC_sim: - stage: test - extends: - - .RIVIERA-PRO - needs: - - job: Scripts - artifacts: true - - job: RIVIERA_PoC_run - artifacts: true - - job: RIVIERA_OSVVM_sim # avoid license blocking - optional: true - artifacts: false - allow_failure: true # if license is in use - variables: - REGRESSION_STEP: "test" - - -# -------------- -# ---- NVC ----- -# -------------- -.NVC: - image: ${CI_REGISTRY}/docker-images/nvc:latest - extends: - - .run - variables: - SIMULATOR: "NVC" - -NVC_OSVVM_run: - stage: build_osvvm - extends: - - .NVC - needs: - job: Scripts - artifacts: true - variables: - REGRESSION_STEP: "osvvm" - -NVC_PoC_run: - stage: build_poc - extends: - - .NVC - needs: - - job: Scripts - artifacts: true - - job: NVC_OSVVM_run - artifacts: true - variables: - REGRESSION_STEP: "poc" - -.NVC_OSVVM_sim: - stage: test - extends: - - .NVC - needs: - - job: Scripts - artifacts: - - job: NVC_OSVVM_run - artifacts: true - only: - - main - - master - - dev - variables: - REGRESSION_STEP: "osvvm_test" - -NVC_PoC_sim: - stage: test - extends: - - .NVC - needs: - - job: Scripts - artifacts: true - - job: NVC_PoC_run - artifacts: true variables: REGRESSION_STEP: "test" - # -------------------------- # ----- Documentation ------ # -------------------------- MergeReports: + stage: Documentation image: ${CI_REGISTRY}/docker-images/base-image:alpine - stage: documentation needs: - - job: GHDL_PoC_sim - artifacts: true - - job: RIVIERA_PoC_sim - artifacts: true - - job: NVC_PoC_sim + - job: PoC-sim artifacts: true before_script: - pip install pyEDAA.Reports script: - mkdir -p report/unit - pyedaa-reports -v unittest "--merge=Any-JUnit:temp/junit/*.xml" "--output=pyTest-JUnit:report/unit/unittest.xml" - - mv temp/junit/${SIMULATOR_PAGES}-PoC.yml report/unit/osvvmreport.yml artifacts: paths: - report/unit Sphinx: + stage: Documentation image: ${CI_REGISTRY}/docker-images/base-image:alpine - stage: documentation needs: - job: MergeReports artifacts: true @@ -284,6 +167,7 @@ Sphinx: - docs/_build/${SPHINX_BUILDER} MikTeX: + stage: Documentation image: ${CI_REGISTRY}/docker-images/miktex:sphinx needs: - job: Sphinx @@ -291,7 +175,6 @@ MikTeX: matrix: - SPHINX_BUILDER: "latex" artifacts: true - stage: documentation script: - cd docs/_build/latex - exec-LaTeX.sh --xelatex "PoC.tex" @@ -306,9 +189,28 @@ MikTeX: # ------------------ # ----- Pages ------ # ------------------ -.pages: +pages: + stage: GitLabPages image: ${CI_REGISTRY}/docker-images/base-image:alpine - stage: pages + parallel: + matrix: + - IMAGE: "nvc" + VERSION: "latest" + - IMAGE: "ghdl" + VERSION: "llvm" + needs: + - job: PoC-sim # main only + artifacts: true + parallel: + matrix: + - IMAGE: $[[ matrix.IMAGE ]] + VERSION: $[[ matrix.VERSION ]] + optional: true + rules: + - if: > + $SIMULATOR_PAGES == "$[[ matrix.IMAGE ]]" && + $CI_PIPELINE_SOURCE == "push" && + $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ variables: GIT_SUBMODULE_STRATEGY: normal pages: true @@ -316,7 +218,7 @@ MikTeX: - apk update - apk add tree script: - - CopyDir docs/_build/html public + - CopyDir docs/_build/html public #- CopyFile PoC.pdf public - tree public after_script: @@ -324,50 +226,3 @@ MikTeX: artifacts: paths: - public - - -pagesGHDL: - rules: - - if: > - $SIMULATOR_PAGES == "GHDL" && - $CI_PIPELINE_SOURCE == "push" && - $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ - needs: - - job: GHDL_OSVVM_sim # main only - artifacts: true - optional: true - - job: GHDL_PoC_sim - artifacts: true - optional: true - extends: - - .pages - -pagesRiviera: - rules: - - if: > - $SIMULATOR_PAGES == "Riviera-PRO" && - $CI_PIPELINE_SOURCE == "push" && - $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ - needs: - - job: RIVIERA_PoC_sim # inherits artifacts from previous jobs - artifacts: true - optional: true - extends: - - .pages - -pagesNVC: - extends: - - .pages - rules: - - if: > - $SIMULATOR_PAGES == "NVC" && - $CI_PIPELINE_SOURCE == "push" - needs: - - job: NVC_OSVVM_sim - artifacts: true - optional: true - - job: NVC_PoC_sim - artifacts: true - optional: true - - job: Sphinx - artifacts: true From 4b299cafabba45f0cce90433c494368201d2475c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 22:08:22 +0200 Subject: [PATCH 14/18] Fixed 'ram' signals to be VHDL-2008 compliant. --- src/mem/ocram/ocram_SimpleDualPort.vhdl | 4 ++-- src/mem/ocram/ocram_SinglePort.vhdl | 4 ++-- src/mem/ocram/ocram_TrueDualPort.vhdl | 4 ++-- src/mem/ocrom/ocrom_DualPort.vhdl | 4 ++-- src/mem/ocrom/ocrom_SinglePort.vhdl | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mem/ocram/ocram_SimpleDualPort.vhdl b/src/mem/ocram/ocram_SimpleDualPort.vhdl index 6bec0bd4c..253c11d98 100644 --- a/src/mem/ocram/ocram_SimpleDualPort.vhdl +++ b/src/mem/ocram/ocram_SimpleDualPort.vhdl @@ -84,7 +84,7 @@ end entity; architecture rtl of ocram_SimpleDualPort is - constant DEPTH : positive := 2**ADDRESS_BITS; + constant WORDS : positive := 2**ADDRESS_BITS; begin gen: if not SIMULATION and ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate @@ -99,7 +99,7 @@ begin -- With two different clocks, synthesis complains about an undefined -- read-write behavior, that can be ignored. - signal ram : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); + signal ram : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := mem_InitMemory(FILENAME, WORDS, DATA_BITS); attribute ramstyle of ram : signal is get_ramstyle_string(RAM_TYPE); attribute ram_style of ram : signal is get_ram_style_string(RAM_TYPE); diff --git a/src/mem/ocram/ocram_SinglePort.vhdl b/src/mem/ocram/ocram_SinglePort.vhdl index ab15f4da1..a99c0dc4b 100644 --- a/src/mem/ocram/ocram_SinglePort.vhdl +++ b/src/mem/ocram/ocram_SinglePort.vhdl @@ -80,11 +80,11 @@ end entity; architecture rtl of ocram_SinglePort is - constant DEPTH : positive := 2**ADDRESS_BITS; + constant WORDS : positive := 2**ADDRESS_BITS; begin gen: if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate - signal ram : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); + signal ram : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := mem_InitMemory(FILENAME, WORDS, DATA_BITS); signal a_reg : unsigned(ADDRESS_BITS-1 downto 0); begin diff --git a/src/mem/ocram/ocram_TrueDualPort.vhdl b/src/mem/ocram/ocram_TrueDualPort.vhdl index fdf6dcfc1..89aea2261 100644 --- a/src/mem/ocram/ocram_TrueDualPort.vhdl +++ b/src/mem/ocram/ocram_TrueDualPort.vhdl @@ -102,11 +102,11 @@ end entity; architecture rtl of ocram_TrueDualPort is - constant DEPTH : positive := 2**ADDRESS_BITS; + constant WORDS : positive := 2**ADDRESS_BITS; begin gen: if not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate - signal ram : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); + signal ram : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := mem_InitMemory(FILENAME, WORDS, DATA_BITS); signal a1_reg : unsigned(ADDRESS_BITS-1 downto 0) := (others => 'U'); signal a2_reg : unsigned(ADDRESS_BITS-1 downto 0) := (others => 'U'); diff --git a/src/mem/ocrom/ocrom_DualPort.vhdl b/src/mem/ocrom/ocrom_DualPort.vhdl index a9b3be5ef..060d302e5 100644 --- a/src/mem/ocrom/ocrom_DualPort.vhdl +++ b/src/mem/ocrom/ocrom_DualPort.vhdl @@ -73,13 +73,13 @@ end entity; architecture rtl of ocrom_DualPort is - constant DEPTH : positive := 2**ADDRESS_BITS; + constant WORDS : positive := 2**ADDRESS_BITS; begin assert (str_length(FILENAME) /= 0) report "Do you really want to generate a block of zeros?" severity FAILURE; gen: if gInfer: (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_XILINX) generate - constant rom : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); + constant rom : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := mem_InitMemory(FILENAME, WORDS, DATA_BITS); signal a1_reg : unsigned(ADDRESS_BITS-1 downto 0); signal a2_reg : unsigned(ADDRESS_BITS-1 downto 0); diff --git a/src/mem/ocrom/ocrom_SinglePort.vhdl b/src/mem/ocrom/ocrom_SinglePort.vhdl index 70d497279..cfdecfe96 100644 --- a/src/mem/ocrom/ocrom_SinglePort.vhdl +++ b/src/mem/ocrom/ocrom_SinglePort.vhdl @@ -61,13 +61,13 @@ end entity; architecture rtl of ocrom_SinglePort is - constant DEPTH : positive := 2**ADDRESS_BITS; + constant WORDS : positive := 2**ADDRESS_BITS; begin assert (str_length(FILENAME) /= 0) report "Do you really want to generate a block of zeros?" severity FAILURE; gen: if gInfer: (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_XILINX) generate - constant rom : T_SLVV := mem_InitMemory(FILENAME, DEPTH, DATA_BITS); + constant rom : T_SLVV(0 to WORDS - 1)(DATA_BITS - 1 downto 0) := mem_InitMemory(FILENAME, WORDS, DATA_BITS); signal a_reg : unsigned(ADDRESS_BITS-1 downto 0); begin process (Clock) From 30bda738ecffba80f3bc0e5b62dc3a7a39f6965d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 22:27:13 +0200 Subject: [PATCH 15/18] Fix GitLab-CI pipeline. --- .editorconfig | 5 +++++ .gitlab-ci.yml | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.editorconfig b/.editorconfig index 356992fe7..9f74e00eb 100644 --- a/.editorconfig +++ b/.editorconfig @@ -15,3 +15,8 @@ trim_trailing_whitespace = false [*.rst] indent_style = space indent_size = 3 + +[*.{yml,yaml}] +indent_style = space +indent_size = 2 + diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0395bbd08..f159a4aa4 100755 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -27,11 +27,12 @@ variables: - mkdir -p temp/junit - CopyFile temp/${SIMULATOR_TOOL}/*/*.xml "temp/junit" - CopyFile temp/${SIMULATOR_TOOL}/*/*.yml "temp/junit" + - tree temp artifacts: paths: - temp/[GNR]* - temp/junit - - lib/osvvm/*_generated.vhd + - lib/osvvm/*_generated.vhd reports: junit: "temp/junit/*.xml" expire_in: 1 week From 47e2805b9bd04f7538276bce18e5cddab2d1e009 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 19 Jun 2026 22:37:12 +0200 Subject: [PATCH 16/18] Disabled INFO and PASSED messages. Removed trailing whitespaces. --- src/fifo/fifo_Stage.vhdl | 2 +- src/mem/ocram/ocram.pkg.vhdl | 2 +- src/mem/ocrom/ocrom.pkg.vhdl | 2 +- .../Adder_Wide/arith_Adder_Wide_Simple.vhdl | 2 +- .../arith_Adder_Wide_TestController.vhdl | 2 +- .../arith_CarryChain_inc_Simple.vhdl | 4 +- .../arith_Convert_Binary2BCD_Simple.vhdl | 6 +- ...ith_Convert_Binary2BCD_TestController.vhdl | 6 +- .../Counter_BCD/arith_Counter_BCD_Simple.vhdl | 2 +- .../arith_Counter_BCD_TestController.vhdl | 2 +- .../arith_Counter_Free_Simple.vhdl | 6 +- .../arith_Counter_Gray_Simple.vhdl | 8 +-- .../arith_Counter_Ring_Simple.vhdl | 4 +- tb/arith/FirstOne/arith_FirstOne_Simple.vhdl | 16 ++--- .../arith_FirstOne_TestController.vhdl | 2 +- tb/arith/Same/arith_Same_Simple.vhdl | 4 +- .../arith_Shifter_Barrel_Simple.vhdl | 10 +-- .../SquareRoot/arith_SquareRoot_Simple.vhdl | 20 +++--- tb/arith/cca/arith_cca_Simple.vhdl | 4 +- tb/bus/axi4/Mux/TC_SimpleReadWrite.vhdl | 4 +- .../TC_SimpleReadWrite_multiID_randDelay.vhdl | 4 +- tb/bus/axi4lite/Demux/TC_SimpleReadWrite.vhdl | 2 +- .../axi4lite/Demux/TC_SimpleReadWrite_02.vhdl | 2 +- ...i4lite_HighResolutionClock_correction.vhdl | 14 ++-- .../UART/axi4lite_UART_receive_burst.vhdl | 69 ++++++++++--------- .../UART/axi4lite_UART_receive_parity.vhdl | 20 +++--- tb/misc/clock/clock_HighResolution_tc.vhdl | 6 +- tb/sync/Bits/sync_Bits_Simple.vhdl | 22 +++--- tb/sync/Command/sync_Command_Simple.vhdl | 6 +- tb/sync/Reset/sync_Reset_Simple.vhdl | 4 +- tb/sync/Strobe/sync_Strobe_Simple.vhdl | 6 +- tb/sync/Vector/sync_Vector_Simple.vhdl | 6 +- 32 files changed, 135 insertions(+), 134 deletions(-) diff --git a/src/fifo/fifo_Stage.vhdl b/src/fifo/fifo_Stage.vhdl index eac108050..5f236987c 100644 --- a/src/fifo/fifo_Stage.vhdl +++ b/src/fifo/fifo_Stage.vhdl @@ -105,7 +105,7 @@ begin end if; end if; end process; - + process (Clock) begin if rising_edge(Clock) then diff --git a/src/mem/ocram/ocram.pkg.vhdl b/src/mem/ocram/ocram.pkg.vhdl index 95aba6d26..4236f13b4 100644 --- a/src/mem/ocram/ocram.pkg.vhdl +++ b/src/mem/ocram/ocram.pkg.vhdl @@ -111,7 +111,7 @@ package ocram is PortA_Address : in unsigned(ADDRESS_BITS-1 downto 0); PortA_DataIn : in std_logic_vector(DATA_BITS-1 downto 0); PortA_DataOut : out std_logic_vector(DATA_BITS-1 downto 0); - + PortB_Clock : in std_logic; PortB_ClockEnable : in std_logic; PortB_Address : in unsigned(ADDRESS_BITS-1 downto 0); diff --git a/src/mem/ocrom/ocrom.pkg.vhdl b/src/mem/ocrom/ocrom.pkg.vhdl index a5e566709..3b1841d19 100644 --- a/src/mem/ocrom/ocrom.pkg.vhdl +++ b/src/mem/ocrom/ocrom.pkg.vhdl @@ -62,7 +62,7 @@ package ocrom is PortA_ClockEnable : in std_logic; PortA_Address : in unsigned(ADDRESS_BITS-1 downto 0); PortA_DataOut : out std_logic_vector(DATA_BITS-1 downto 0); - + PortB_Clock : in std_logic; PortB_ClockEnable : in std_logic; PortB_Address : in unsigned(ADDRESS_BITS-1 downto 0); diff --git a/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl b/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl index f2844cbce..cb35df6f1 100644 --- a/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl +++ b/tb/arith/Adder_Wide/arith_Adder_Wide_Simple.vhdl @@ -72,7 +72,7 @@ begin CheckerProc: process constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID); - + variable expected : natural; variable actual_sum : unsigned(9 downto 0); begin diff --git a/tb/arith/Adder_Wide/arith_Adder_Wide_TestController.vhdl b/tb/arith/Adder_Wide/arith_Adder_Wide_TestController.vhdl index d159b0e06..561d9a314 100644 --- a/tb/arith/Adder_Wide/arith_Adder_Wide_TestController.vhdl +++ b/tb/arith/Adder_Wide/arith_Adder_Wide_TestController.vhdl @@ -40,7 +40,7 @@ entity arith_Adder_Wide_TestController is port ( Clock : in std_logic; Reset : in std_logic; - + -- DUT ports (arrays for all variants) a : out word; b : out word; diff --git a/tb/arith/CarryChain_inc/arith_CarryChain_inc_Simple.vhdl b/tb/arith/CarryChain_inc/arith_CarryChain_inc_Simple.vhdl index 1015ee399..24c0089dd 100644 --- a/tb/arith/CarryChain_inc/arith_CarryChain_inc_Simple.vhdl +++ b/tb/arith/CarryChain_inc/arith_CarryChain_inc_Simple.vhdl @@ -74,7 +74,7 @@ begin -- Test with CIn = 1 (increment) CIn <= '1'; - + X <= x"00"; wait for 1 ns; expected := to_unsigned(1, Y'length); @@ -102,7 +102,7 @@ begin -- Test with CIn = 0 (no increment, just pass through) CIn <= '0'; - + X <= x"00"; wait for 1 ns; expected := to_unsigned(0, Y'length); diff --git a/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_Simple.vhdl b/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_Simple.vhdl index 00c5a4e04..ea37af588 100644 --- a/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_Simple.vhdl +++ b/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_Simple.vhdl @@ -43,7 +43,7 @@ use PoC.physical.all; architecture Simple of arith_Convert_Binary2BCD_TestController is constant TCID : AlertLogIDType := NewID("ConvBin2BCDTest"); signal TestDone : integer_barrier := 1; - + constant INPUT_1 : integer := 38442113; constant INPUT_2 : integer := 78734531; constant INPUT_3 : integer := 14902385; @@ -74,8 +74,8 @@ begin begin SetTestName("arith_Convert_Binary2BCD_Simple"); - SetLogEnable(PASSED, TRUE); - SetLogEnable(INFO, TRUE); + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, FALSE); SetLogEnable(DEBUG, FALSE); wait for 0 ns; wait for 0 ns; diff --git a/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_TestController.vhdl b/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_TestController.vhdl index b4541c8cc..6ec0bed59 100644 --- a/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_TestController.vhdl +++ b/tb/arith/Convert_Binary2BCD/arith_Convert_Binary2BCD_TestController.vhdl @@ -46,14 +46,14 @@ entity arith_Convert_Binary2BCD_TestController is port ( Clock : in std_logic; Reset : in std_logic; - + -- DUT signals Start : out std_logic; - + Conv1_Binary : out std_logic_vector(CONV1_BITS - 1 downto 0); Conv1_BCDDigits : in T_BCD_VECTOR(CONV1_DIGITS - 1 downto 0); Conv1_Sign : in std_logic; - + Conv2_Binary : out std_logic_vector(CONV2_BITS - 1 downto 0); Conv2_BCDDigits : in T_BCD_VECTOR(CONV2_DIGITS - 1 downto 0); Conv2_Sign : in std_logic diff --git a/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl b/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl index 0a5d165f6..2a5349eb4 100644 --- a/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl +++ b/tb/arith/Counter_BCD/arith_Counter_BCD_Simple.vhdl @@ -40,7 +40,7 @@ use PoC.physical.all; architecture Simple of arith_Counter_BCD_TestController is constant TCID : AlertLogIDType := NewID("CntBCDTest"); - + signal TestDone : integer_barrier := 1; begin diff --git a/tb/arith/Counter_BCD/arith_Counter_BCD_TestController.vhdl b/tb/arith/Counter_BCD/arith_Counter_BCD_TestController.vhdl index 8a46b6e68..9dab19848 100644 --- a/tb/arith/Counter_BCD/arith_Counter_BCD_TestController.vhdl +++ b/tb/arith/Counter_BCD/arith_Counter_BCD_TestController.vhdl @@ -43,7 +43,7 @@ entity arith_Counter_BCD_TestController is Clock : in std_logic; Reset : in std_logic; Reset_aux : out std_logic; - + -- DUT signals arith_Counter_BCD inc : out std_logic; Value : in T_BCD_VECTOR(DIGITS - 1 downto 0) diff --git a/tb/arith/Counter_Free/arith_Counter_Free_Simple.vhdl b/tb/arith/Counter_Free/arith_Counter_Free_Simple.vhdl index 398471492..f577c0212 100644 --- a/tb/arith/Counter_Free/arith_Counter_Free_Simple.vhdl +++ b/tb/arith/Counter_Free/arith_Counter_Free_Simple.vhdl @@ -71,7 +71,7 @@ begin begin -- Initialize control signal inc <= '0'; - + wait until Reset = '0'; WaitForClock(Clock); @@ -79,7 +79,7 @@ begin WaitForClock(Clock); inc <= '1'; WaitForClock(Clock); - + -- Should not assert strobe for first DIVIDER-1 cycles for i in 1 to DIVIDER-1 loop AffirmIf(ProcID, stb = '0', "Strobe should be low before divider count reached (cycle " & integer'image(i) & ")"); @@ -92,7 +92,7 @@ begin -- Next cycle, strobe should be low again and start new count AffirmIf(ProcID, stb = '0', "Strobe should return to low after assertion"); - + -- Test another cycle for i in 1 to DIVIDER-2 loop WaitForClock(Clock); diff --git a/tb/arith/Counter_Gray/arith_Counter_Gray_Simple.vhdl b/tb/arith/Counter_Gray/arith_Counter_Gray_Simple.vhdl index ab03557e4..f0d82920e 100644 --- a/tb/arith/Counter_Gray/arith_Counter_Gray_Simple.vhdl +++ b/tb/arith/Counter_Gray/arith_Counter_Gray_Simple.vhdl @@ -67,19 +67,19 @@ begin CheckerProc: process constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID); - + -- Gray code sequence for 4 bits: 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000 type gray_sequence_type is array (0 to 15) of std_logic_vector(3 downto 0); constant GRAY_SEQ : gray_sequence_type := ( "0000", "0001", "0011", "0010", "0110", "0111", "0101", "0100", "1100", "1101", "1111", "1110", "1010", "1011", "1001", "1000" ); - + begin -- Initialize control signals inc <= '0'; dec <= '0'; - + wait until Reset = '0'; WaitForClock(Clock); @@ -94,7 +94,7 @@ begin wait until falling_edge(Clock); inc <= '0'; WaitForClock(Clock); - AffirmIf(ProcID, val = GRAY_SEQ(i), + AffirmIf(ProcID, val = GRAY_SEQ(i), "Gray increment step " & integer'image(i) & ": expected " & to_string(GRAY_SEQ(i))); end loop; diff --git a/tb/arith/Counter_Ring/arith_Counter_Ring_Simple.vhdl b/tb/arith/Counter_Ring/arith_Counter_Ring_Simple.vhdl index 7bde92fea..8aa2b289e 100644 --- a/tb/arith/Counter_Ring/arith_Counter_Ring_Simple.vhdl +++ b/tb/arith/Counter_Ring/arith_Counter_Ring_Simple.vhdl @@ -72,7 +72,7 @@ begin -- Initialize control signals inc <= '0'; dec <= '0'; - + wait until Reset = '0'; WaitForClock(Clock); @@ -82,7 +82,7 @@ begin -- Test increment (ring counter shift left) -- Use same pattern as BCD counter test: pulse inc for each increment - + -- First increment wait until falling_edge(Clock); inc <= '1'; diff --git a/tb/arith/FirstOne/arith_FirstOne_Simple.vhdl b/tb/arith/FirstOne/arith_FirstOne_Simple.vhdl index c8f9ee86e..60614b4f0 100644 --- a/tb/arith/FirstOne/arith_FirstOne_Simple.vhdl +++ b/tb/arith/FirstOne/arith_FirstOne_Simple.vhdl @@ -81,14 +81,14 @@ begin -- Test with tin = '0': no token input, should have no grants tin <= '0'; WaitForClock(Clock); - AffirmIf(ProcID, + AffirmIf(ProcID, grnt = (grnt'range => '0') and tout = '0', "Unexpected token output with tin='0' in testcase #" & integer'image(i)); -- Test with tin = '1': token input, check grant pattern tin <= '1'; wait until falling_edge(Clock); - + -- Check each bit of grant output for j in 0 to N-1 loop -- Grant(j) should be '1' if and only if: @@ -98,17 +98,17 @@ begin -- For bit 0, only check if rqst(0) is '1' AffirmIf(ProcID, (grnt(j) = '1') = (rqst(j) = '1'), - "Wrong grant for bit " & integer'image(j) & + "Wrong grant for bit " & integer'image(j) & " in testcase #" & integer'image(i) & - " (rqst=" & to_hxstring(rqst) & + " (rqst=" & to_hxstring(rqst) & ", grnt=" & to_hxstring(grnt) & ")"); else -- For higher bits, check if this is the first '1' from the right AffirmIf(ProcID, (grnt(j) = '1') = ((rqst(j) = '1') and (rqst(j-1 downto 0) = (j-1 downto 0 => '0'))), - "Wrong grant for bit " & integer'image(j) & + "Wrong grant for bit " & integer'image(j) & " in testcase #" & integer'image(i) & - " (rqst=" & to_hxstring(rqst) & + " (rqst=" & to_hxstring(rqst) & ", grnt=" & to_hxstring(grnt) & ")"); end if; end loop; @@ -117,7 +117,7 @@ begin AffirmIf(ProcID, (tout = '1') = (rqst = (N-1 downto 0 => '0')), "Wrong tout in testcase #" & integer'image(i) & - " (rqst=" & to_hxstring(rqst) & + " (rqst=" & to_hxstring(rqst) & ", tout=" & std_logic'image(tout) & ")"); -- Verify binary output bin points to the granted bit @@ -132,7 +132,7 @@ begin end if; end loop; end if; - + end loop; Log(ProcID, "Exhaustively tested all " & integer'image(2**N) & " request patterns", INFO); diff --git a/tb/arith/FirstOne/arith_FirstOne_TestController.vhdl b/tb/arith/FirstOne/arith_FirstOne_TestController.vhdl index 054b7707d..05a241ae9 100644 --- a/tb/arith/FirstOne/arith_FirstOne_TestController.vhdl +++ b/tb/arith/FirstOne/arith_FirstOne_TestController.vhdl @@ -41,7 +41,7 @@ entity arith_FirstOne_TestController is port ( Clock : in std_logic; Reset : in std_logic; - + -- DUT signals arith_FirstOne tin : out std_logic; rqst : out std_logic_vector(N-1 downto 0); diff --git a/tb/arith/Same/arith_Same_Simple.vhdl b/tb/arith/Same/arith_Same_Simple.vhdl index 518b48769..576473f55 100644 --- a/tb/arith/Same/arith_Same_Simple.vhdl +++ b/tb/arith/Same/arith_Same_Simple.vhdl @@ -73,7 +73,7 @@ begin -- Test with guard = 1 (active) g <= '1'; - + -- Test all zeros x <= (x'range => '0'); WaitForClock(Clock); @@ -103,7 +103,7 @@ begin -- Test with guard = 0 (inactive, should always return 0) g <= '0'; - + x <= (x'range => '0'); WaitForClock(Clock); AffirmIf(ProcID, y = '0', "Guard=0 should return '0' even for all zeros"); diff --git a/tb/arith/Shifter_Barrel/arith_Shifter_Barrel_Simple.vhdl b/tb/arith/Shifter_Barrel/arith_Shifter_Barrel_Simple.vhdl index 311edd58b..aadcd81c0 100644 --- a/tb/arith/Shifter_Barrel/arith_Shifter_Barrel_Simple.vhdl +++ b/tb/arith/Shifter_Barrel/arith_Shifter_Barrel_Simple.vhdl @@ -76,7 +76,7 @@ begin ShiftRotate <= '0'; -- Shift mode LeftRight <= '0'; -- Left ArithmeticLogic <= '0'; -- Logic (doesn't matter for left shift) - + Input <= "10110011"; ShiftAmount <= "001"; -- Shift by 1 wait for 1 ns; @@ -93,7 +93,7 @@ begin ShiftRotate <= '0'; -- Shift mode LeftRight <= '1'; -- Right ArithmeticLogic <= '1'; -- Logic - + Input <= "10110011"; ShiftAmount <= "001"; -- Shift by 1 wait for 1 ns; @@ -110,7 +110,7 @@ begin ShiftRotate <= '0'; -- Shift mode LeftRight <= '1'; -- Right ArithmeticLogic <= '0'; -- Arithmetic - + Input <= "10110011"; -- Negative number ShiftAmount <= "001"; -- Shift by 1 wait for 1 ns; @@ -126,7 +126,7 @@ begin -- Test Rotate Left (RL) ShiftRotate <= '1'; -- Rotate mode LeftRight <= '0'; -- Left - + Input <= "10110011"; ShiftAmount <= "001"; -- Rotate by 1 wait for 1 ns; @@ -142,7 +142,7 @@ begin -- Test Rotate Right (RR) ShiftRotate <= '1'; -- Rotate mode LeftRight <= '1'; -- Right - + Input <= "10110011"; ShiftAmount <= "001"; -- Rotate by 1 wait for 1 ns; diff --git a/tb/arith/SquareRoot/arith_SquareRoot_Simple.vhdl b/tb/arith/SquareRoot/arith_SquareRoot_Simple.vhdl index b10e86d69..46de7ef10 100644 --- a/tb/arith/SquareRoot/arith_SquareRoot_Simple.vhdl +++ b/tb/arith/SquareRoot/arith_SquareRoot_Simple.vhdl @@ -67,12 +67,12 @@ begin CheckerProc: process constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID); - + type test_vector is record input : natural; expected : natural; end record; - + type test_array is array (natural range <>) of test_vector; constant test_cases : test_array := ( (0, 0), -- sqrt(0) = 0 @@ -93,7 +93,7 @@ begin (225, 15), -- sqrt(225) = 15 (255, 15) -- sqrt(255) = 15 ); - + begin wait until Reset = '0'; WaitForClock(Clock); @@ -104,21 +104,21 @@ begin start <= '1'; WaitForClock(Clock); start <= '0'; - + -- Wait for computation to start (rdy goes low) wait until rdy = '0'; -- Wait for computation to complete (rdy goes high) wait until rdy = '1'; WaitForClock(Clock); - + -- Check result - AffirmIf(ProcID, - unsigned(sqrt) = test_cases(i).expected, - "sqrt(" & integer'image(test_cases(i).input) & ") = " & - integer'image(test_cases(i).expected) & + AffirmIf(ProcID, + unsigned(sqrt) = test_cases(i).expected, + "sqrt(" & integer'image(test_cases(i).input) & ") = " & + integer'image(test_cases(i).expected) & ", got " & integer'image(to_integer(unsigned(sqrt))) ); - + WaitForClock(Clock); end loop; diff --git a/tb/arith/cca/arith_cca_Simple.vhdl b/tb/arith/cca/arith_cca_Simple.vhdl index 3b12502ec..3c73a6202 100644 --- a/tb/arith/cca/arith_cca_Simple.vhdl +++ b/tb/arith/cca/arith_cca_Simple.vhdl @@ -75,7 +75,7 @@ begin -- Test basic addition without carry c <= '0'; - + a <= x"00"; b <= x"00"; wait for 1 ns; @@ -108,7 +108,7 @@ begin -- Test addition with carry = 1 c <= '1'; - + a <= x"00"; b <= x"00"; wait for 1 ns; diff --git a/tb/bus/axi4/Mux/TC_SimpleReadWrite.vhdl b/tb/bus/axi4/Mux/TC_SimpleReadWrite.vhdl index f5022557f..7b324f1b5 100644 --- a/tb/bus/axi4/Mux/TC_SimpleReadWrite.vhdl +++ b/tb/bus/axi4/Mux/TC_SimpleReadWrite.vhdl @@ -47,8 +47,8 @@ begin TranscriptOpen; SetTranscriptMirror(TRUE); - SetLogEnable(PASSED, TRUE); -- Enable PASSED logs - SetLogEnable(INFO, TRUE); -- Enable INFO logs + SetLogEnable(PASSED, FALSE); -- Enable PASSED logs + SetLogEnable(INFO, FALSE); -- Enable INFO logs -- Wait for testbench initialization diff --git a/tb/bus/axi4/Mux/TC_SimpleReadWrite_multiID_randDelay.vhdl b/tb/bus/axi4/Mux/TC_SimpleReadWrite_multiID_randDelay.vhdl index dc5404b28..45c5f77bb 100644 --- a/tb/bus/axi4/Mux/TC_SimpleReadWrite_multiID_randDelay.vhdl +++ b/tb/bus/axi4/Mux/TC_SimpleReadWrite_multiID_randDelay.vhdl @@ -45,8 +45,8 @@ begin TranscriptOpen; SetTranscriptMirror(TRUE); - SetLogEnable(PASSED, FALSE); -- Enable PASSED logs - SetLogEnable(INFO, TRUE); -- Enable INFO logs + SetLogEnable(PASSED, FALSE); -- Enable PASSED logs + SetLogEnable(INFO, FALSE); -- Enable INFO logs -- Wait for testbench initialization diff --git a/tb/bus/axi4lite/Demux/TC_SimpleReadWrite.vhdl b/tb/bus/axi4lite/Demux/TC_SimpleReadWrite.vhdl index b4ba7e8ac..159684d46 100644 --- a/tb/bus/axi4lite/Demux/TC_SimpleReadWrite.vhdl +++ b/tb/bus/axi4lite/Demux/TC_SimpleReadWrite.vhdl @@ -38,7 +38,7 @@ begin SetTranscriptMirror(TRUE); SetLogEnable(PASSED, FALSE); -- Enable PASSED logs - SetLogEnable(INFO, TRUE); -- Enable INFO logs + SetLogEnable(INFO, FALSE); -- Enable INFO logs -- Wait for testbench initialization diff --git a/tb/bus/axi4lite/Demux/TC_SimpleReadWrite_02.vhdl b/tb/bus/axi4lite/Demux/TC_SimpleReadWrite_02.vhdl index ef74d92d2..0afb0fb26 100644 --- a/tb/bus/axi4lite/Demux/TC_SimpleReadWrite_02.vhdl +++ b/tb/bus/axi4lite/Demux/TC_SimpleReadWrite_02.vhdl @@ -45,7 +45,7 @@ begin SetTranscriptMirror(TRUE); SetLogEnable(PASSED, FALSE); -- Enable PASSED logs - SetLogEnable(INFO, TRUE); -- Enable INFO logs + SetLogEnable(INFO, FALSE); -- Enable INFO logs -- Wait for testbench initialization diff --git a/tb/bus/axi4lite/HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl b/tb/bus/axi4lite/HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl index 3c8bd880b..9312d77e2 100644 --- a/tb/bus/axi4lite/HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl +++ b/tb/bus/axi4lite/HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl @@ -32,8 +32,8 @@ begin begin -- Initialization of test SetTestName("axi4lite_HighResolutionClock_correction"); - SetLogEnable(PASSED, TRUE); --Enable PASSED Logs - SetLogEnable(INFO, TRUE); --Enable INFO Logs + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs -- Wait for testbench Initialization wait for 0 ns; @@ -56,7 +56,7 @@ begin procedure LoadNanoseconds ( signal manager : inout AddressBusRecType; constant Nanoseconds_to_load : natural - ) is + ) is variable ns_value_slv : std_logic_vector(63 downto 0) := to_slv(Nanoseconds_to_load, 64); begin log(""); @@ -90,14 +90,14 @@ begin Read(AXI_Manager, Reg_Nanoseconds_lower, ReadData); time_now_a := now; time_ns_a_l := to_integer(unsigned(ReadData)); - + wait for correction_time; - + Read(AXI_Manager, Reg_Nanoseconds_lower, ReadData); time_now_b := now; time_now_delta := time_now_b - time_now_a; time_now_delta_val := time_now_delta / 1000 ps; - + case config is when "11" => -- increment if correction_threshold = 0 then @@ -123,7 +123,7 @@ begin "Delta: /= " & to_string(delta_expected - 1) & " to " & to_string(delta_expected + 1) & " (expected)" ); end procedure; - + begin wait until Reset = '0'; WaitForClock(AXI_Manager, 2); diff --git a/tb/bus/axi4lite/UART/axi4lite_UART_receive_burst.vhdl b/tb/bus/axi4lite/UART/axi4lite_UART_receive_burst.vhdl index c32477bb6..3b54fb9c3 100644 --- a/tb/bus/axi4lite/UART/axi4lite_UART_receive_burst.vhdl +++ b/tb/bus/axi4lite/UART/axi4lite_UART_receive_burst.vhdl @@ -1,12 +1,12 @@ architecture receive_burst of axi4lite_UART_tc is - subtype UARTDataType is std_logic_vector(7 downto 0); + subtype UARTDataType is std_logic_vector(7 downto 0); alias UARTSequenceType is T_SLVV_8; - alias SB_IDType is OSVVM.ScoreBoardPkg_slv.ScoreboardIdType; + alias SB_IDType is OSVVM.ScoreBoardPkg_slv.ScoreboardIdType; signal UART_receive_SB : SB_IDType; - + constant TestCtrlID : AlertLogIDType := NewID("TestController"); - + constant TestData : UARTSequenceType := (x"5A", -- 1B x"CA",x"FE",x"AF",x"FE", -- 4B x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF", -- 8B @@ -21,7 +21,7 @@ architecture receive_burst of axi4lite_UART_tc is IsOverrun : boolean; end record; type SequencesType is array(natural range <>) of SequenceDescriptionType; - + constant Sequences : SequencesType := ( 0 => ( 1, 1, FALSE, FALSE), 1 => ( 4, 4, FALSE, FALSE), @@ -47,7 +47,7 @@ architecture receive_burst of axi4lite_UART_tc is end loop; return lengths; end function; - + constant TransmitLengths : T_POSVEC := toTransmitLengths(Sequences); constant ReadoutLengths : T_POSVEC := toReadoutLengths(Sequences); @@ -60,9 +60,10 @@ begin begin -- Initialization of test SetTestName("axi4lite_UART_receive_burst"); - SetLogEnable(PASSED, TRUE); --Enable PASSED Logs - SetLogEnable(INFO, TRUE); --Enable INFO Logs - UART_receive_SB <= OSVVM.ScoreBoardPkg_slv.NewID("UART_receive_SB"); + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs + + UART_receive_SB <= OSVVM.ScoreBoardPkg_slv.NewID("UART_receive_SB"); -- Wait for testbench Initialization wait for 0 ns; @@ -81,19 +82,19 @@ begin end process ControlProc; -- Generate transaction for AXI manager - ManagerProc : process + ManagerProc : process constant ProcLogID : AlertLogIDType := NewID("ManagerProc", TestCtrlID); variable AxiManagerLogID : AlertLogIDType; - + constant RX_REG : AXIAddressType := 32x"00"; constant TX_REG : AXIAddressType := 32x"04"; constant STATUS_REG : AXIAddressType := 32x"08"; constant CONTROL_REG : AXIAddressType := 32x"0C"; - + variable ReceivedData : AXIDataType; variable isFull : boolean := true; variable isEmpty : boolean := true; - + -- status reg for rx, bit 5 checks for the Status_RX_Overrun procedure CheckIsEmpty_RX( signal manager : inout AddressBusRecType; @@ -106,7 +107,7 @@ begin isEmpty := Data(0) = '0'; AffirmIf(isEmpty = expected, "EmptyBit: Received: " & to_string(isEmpty), " /= Expected: " & to_string(expected)); end procedure; - + procedure CheckIsFull_RX( signal manager : inout AddressBusRecType; constant expected : in boolean @@ -118,7 +119,7 @@ begin isFull := Data(1) = '1'; AffirmIf(isFull = expected, "FullBit: Received: " & to_string(isFull), " /= Expected: " & to_string(expected)); end procedure; - + procedure CheckIsOverrun_RX( signal manager : inout AddressBusRecType; constant expected : in boolean @@ -130,7 +131,7 @@ begin isOverrun := Data(5) = '1'; AffirmIf(isOverrun = expected, "OverrunBit: Received: " & to_string(isOverrun), " /= Expected: " & to_string(expected)); end procedure; - + procedure CheckIsParity_flag( signal manager : inout AddressBusRecType; constant expected : in boolean @@ -142,21 +143,21 @@ begin parity_error := Data(7) = '1'; AffirmIf(parity_error = expected, "EmptyBit: Received: " & to_string(parity_error), " /= Expected: " & to_string(expected)); end procedure; - + begin - wait until Reset = '0'; - + wait until Reset = '0'; + GetAlertLogID(AXI_Manager, AxiManagerLogID); - SetLogEnable(AxiManagerLogID, INFO, False); - + SetLogEnable(AxiManagerLogID, INFO, False); + for i in ReadoutLengths'range loop WaitForToggle(ReadByteTrigger); - + CheckIsEmpty_RX(AXI_Manager, FALSE); CheckIsParity_flag(AXI_Manager, FALSE); CheckIsFull_RX(AXI_Manager, Sequences(i).IsFull); CheckIsOverrun_RX(AXI_Manager, Sequences(i).IsOverrun); - + log(ProcLogID, "Reading received data sequence " & to_string(i) & " of " & to_string(ReadoutLengths(i)) & " bytes from UART register"); for j in 0 to ReadoutLengths(i) - 1 loop Read(AXI_Manager, RX_REG, ReceivedData); @@ -167,7 +168,7 @@ begin CheckIsFull_RX(AXI_Manager, FALSE); CheckIsOverrun_RX(AXI_Manager, FALSE); end loop; - + wait for 500 us; WaitForBarrier(TestDone); wait; @@ -176,28 +177,28 @@ begin -- Generate transactions for UART transmitter UartTxProc : process constant ProcLogID : AlertLogIDType := NewID("UartTxProc", TestCtrlID); - + procedure UARTSendBurst( - signal uartRec : inout UartRecType; + signal uartRec : inout UartRecType; constant data_array : in UARTSequenceType ) is begin - for i in data_array'range loop - OSVVM.ScoreBoardPkg_slv.Push(UART_receive_SB, data_array(i)); + for i in data_array'range loop + OSVVM.ScoreBoardPkg_slv.Push(UART_receive_SB, data_array(i)); log(ProcLogID, "Sending data of " & to_string(i) & "th byte to AXI RX register"); Send(uartRec, data_array(i)); end loop; - end procedure; + end procedure; begin wait until Reset = '0'; - WaitForClock(UartTxRec, 1); - + WaitForClock(UartTxRec, 1); + for i in TransmitLengths'range loop log("Send test sequence " & to_string(i) & " of " & to_string(TransmitLengths(i)) & " bytes to AXI RX register ..."); UARTSendBurst(UartTxRec, TestData(low(TransmitLengths, i) to high(TransmitLengths, i))); Increment(ReadByteTrigger); end loop; - + WaitForBarrier(TestDone); wait; end process; @@ -207,9 +208,9 @@ begin constant ProcLogID : AlertLogIDType := NewID("UartRxProc", TestCtrlID); begin wait until Reset = '0'; - + log(ProcLogID, "Transmit verification model isn't used in this testcase"); - + WaitForBarrier(TestDone); wait; end process; diff --git a/tb/bus/axi4lite/UART/axi4lite_UART_receive_parity.vhdl b/tb/bus/axi4lite/UART/axi4lite_UART_receive_parity.vhdl index 82e056772..868d74942 100644 --- a/tb/bus/axi4lite/UART/axi4lite_UART_receive_parity.vhdl +++ b/tb/bus/axi4lite/UART/axi4lite_UART_receive_parity.vhdl @@ -16,8 +16,8 @@ begin begin -- Initialization of test SetTestName("axi4lite_UART_receive_parity"); - SetLogEnable(PASSED, TRUE); --Enable PASSED Logs - SetLogEnable(INFO, TRUE); --Enable INFO Logs + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs -- Wait for testbench Initialization wait for 0 ns; @@ -45,9 +45,9 @@ begin begin return 24x"00" & data; end function; - + variable ReceivedData : AXIDataType; - + procedure CheckIsParity_flag( signal manager : inout AddressBusRecType; constant expected : in boolean @@ -59,13 +59,13 @@ begin parity_error := Data(7) = '1'; AffirmIf(parity_error = expected, "EmptyBit: Received: " & to_string(parity_error), " /= Expected: " & to_string(expected)); end procedure; - + begin wait until Reset = '0'; for j in parityerror'range loop WaitForToggle(ReadByteTrigger); CheckIsParity_flag(AXI_Manager, parityerror(j)); - + log("Reading received data byte from UART register ..."); Read(AXI_Manager, RX_REG, ReceivedData); AffirmIf( @@ -85,12 +85,12 @@ begin wait until Reset = '0'; WaitForClock(UartTxRec, 1); - for i in TestData'range loop + for i in TestData'range loop if parityerror(i) then - Send(UartTxRec, TestData(i),UARTTB_PARITY_ERROR); + Send(UartTxRec, TestData(i),UARTTB_PARITY_ERROR); else - Send(UartTxRec, TestData(i)); - end if; + Send(UartTxRec, TestData(i)); + end if; Toggle(ReadByteTrigger); end loop; WaitForBarrier(TestDone); diff --git a/tb/misc/clock/clock_HighResolution_tc.vhdl b/tb/misc/clock/clock_HighResolution_tc.vhdl index b559ee9b4..9e7161061 100644 --- a/tb/misc/clock/clock_HighResolution_tc.vhdl +++ b/tb/misc/clock/clock_HighResolution_tc.vhdl @@ -31,7 +31,7 @@ use PoC.physical.all; use PoC.math.all; use PoC.clock.all; -library OSVVM; +library OSVVM; context OSVVM.OsvvmContext; library osvvm_Axi4; @@ -46,12 +46,12 @@ entity clock_HighResolution_tc is Clock : in std_logic; Reset : in std_logic; AXI_Manager : inout AddressBusRecType; - + Load_nanoseconds : out std_logic; Load_datetime : out std_logic; Nanoseconds_to_load : out unsigned(63 downto 0); Datetime_to_load : out T_CLOCK_Datetime; - + Nanoseconds : in unsigned(63 downto 0); Datetime : in T_CLOCK_Datetime ); diff --git a/tb/sync/Bits/sync_Bits_Simple.vhdl b/tb/sync/Bits/sync_Bits_Simple.vhdl index d4f0d8fcf..7be186a9a 100644 --- a/tb/sync/Bits/sync_Bits_Simple.vhdl +++ b/tb/sync/Bits/sync_Bits_Simple.vhdl @@ -43,7 +43,7 @@ architecture Simple of sync_Bits_TestController is signal TestDone : integer_barrier := 1; constant TCID : AlertLogIDType := NewID("TestCtrl"); - + constant INIT : std_logic_vector(Sync_out'range) := (others => '0'); begin @@ -77,32 +77,32 @@ begin begin -- Initialize Sync_in <= INIT; - + wait until Reset = '0'; WaitForClock(Clock1, 4); -- Toggle input several times with different patterns Sync_in <= "1"; WaitForClock(Clock1, 2); - + Sync_in <= "0"; WaitForClock(Clock1, 2); - + Sync_in <= "1"; WaitForClock(Clock1, 2); - + Sync_in <= "0"; WaitForClock(Clock1, 6); - + Sync_in <= "1"; WaitForClock(Clock1, 16); - + Sync_in <= "0"; WaitForClock(Clock1, 2); - + Sync_in <= "1"; WaitForClock(Clock1, 2); - + Sync_in <= "0"; WaitForClock(Clock1, 6); @@ -116,7 +116,7 @@ begin begin wait until Reset = '0'; WaitForClock(Clock2); - + -- Check initial value AffirmIf(ProcID, Sync_out = INIT, "Initial value should be " & to_string(INIT)); Sync_out_old := Sync_out; @@ -131,7 +131,7 @@ begin end loop; -- Should see 8 toggle events based on stimuli - AffirmIf(ProcID, toggled = 8, + AffirmIf(ProcID, toggled = 8, "Expected 8 toggle events, got " & integer'image(toggled)); WaitForBarrier(TestDone); diff --git a/tb/sync/Command/sync_Command_Simple.vhdl b/tb/sync/Command/sync_Command_Simple.vhdl index 6cd7afbfd..678a08ea3 100644 --- a/tb/sync/Command/sync_Command_Simple.vhdl +++ b/tb/sync/Command/sync_Command_Simple.vhdl @@ -43,7 +43,7 @@ architecture Simple of sync_Command_TestController is signal TestDone : integer_barrier := 1; constant TCID : AlertLogIDType := NewID("TestCtrl"); - + constant INIT : std_logic_vector(Output'range) := (others => '0'); begin @@ -77,7 +77,7 @@ begin begin -- Initialize Input <= INIT; - + WaitForClock(Clock1, 4); -- Send "01" command @@ -138,7 +138,7 @@ begin end loop; -- Should see at least 3 Changed events based on stimuli - AffirmIf(ProcID, ChangedCnt >= 3, + AffirmIf(ProcID, ChangedCnt >= 3, "Expected at least 3 Changed events, got " & integer'image(ChangedCnt)); WaitForBarrier(TestDone); diff --git a/tb/sync/Reset/sync_Reset_Simple.vhdl b/tb/sync/Reset/sync_Reset_Simple.vhdl index 083efc78b..151fb7945 100644 --- a/tb/sync/Reset/sync_Reset_Simple.vhdl +++ b/tb/sync/Reset/sync_Reset_Simple.vhdl @@ -75,7 +75,7 @@ begin begin -- Initialize Input <= '0'; - + WaitForClock(Clock1, 4); -- Short reset pulse @@ -130,7 +130,7 @@ begin end loop; -- Should see at least 1 Output high transition based on stimuli - AffirmIf(ProcID, OutputHighCnt >= 1, + AffirmIf(ProcID, OutputHighCnt >= 1, "Expected at least 1 Output high transition, got " & integer'image(OutputHighCnt)); WaitForBarrier(TestDone); diff --git a/tb/sync/Strobe/sync_Strobe_Simple.vhdl b/tb/sync/Strobe/sync_Strobe_Simple.vhdl index 7e729a37d..a6ceb949f 100644 --- a/tb/sync/Strobe/sync_Strobe_Simple.vhdl +++ b/tb/sync/Strobe/sync_Strobe_Simple.vhdl @@ -43,7 +43,7 @@ architecture Simple of sync_Strobe_TestController is signal TestDone : integer_barrier := 1; constant TCID : AlertLogIDType := NewID("TestCtrl"); - + constant INIT : std_logic_vector(Output'range) := (others => '0'); begin @@ -77,7 +77,7 @@ begin begin -- Initialize Input <= INIT; - + WaitForClock(Clock1, 4); -- First strobe pulse @@ -136,7 +136,7 @@ begin end loop; -- Should see at least 1 output strobe based on stimuli - AffirmIf(ProcID, StrobeCnt >= 1, + AffirmIf(ProcID, StrobeCnt >= 1, "Expected at least 1 output strobe, got " & integer'image(StrobeCnt)); WaitForBarrier(TestDone); diff --git a/tb/sync/Vector/sync_Vector_Simple.vhdl b/tb/sync/Vector/sync_Vector_Simple.vhdl index be78965fc..ae3123c6d 100644 --- a/tb/sync/Vector/sync_Vector_Simple.vhdl +++ b/tb/sync/Vector/sync_Vector_Simple.vhdl @@ -43,7 +43,7 @@ architecture Simple of sync_Vector_TestController is signal TestDone : integer_barrier := 1; constant TCID : AlertLogIDType := NewID("TestCtrl"); - + constant INIT : std_logic_vector(Output'range) := (others => '0'); begin @@ -77,7 +77,7 @@ begin begin -- Initialize Input <= INIT; - + WaitForClock(Clock1, 4); -- Send "01" vector @@ -133,7 +133,7 @@ begin end loop; -- Should see at least 2 Changed events based on stimuli - AffirmIf(ProcID, ChangedCnt >= 2, + AffirmIf(ProcID, ChangedCnt >= 2, "Expected at least 2 Changed events, got " & integer'image(ChangedCnt)); WaitForBarrier(TestDone); From 8b1f5492a101a9d9c71bb8f09ecb3ff102dce85e Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Fri, 19 Jun 2026 23:03:09 +0200 Subject: [PATCH 17/18] * print message if local-file generation is skipped * remove spaces for puts prefix for disabled and duplicate procedure --- regression.tcl | 2 ++ tools/poc.tcl | 7 ++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/regression.tcl b/regression.tcl index 1792b5241..9f4629e71 100644 --- a/regression.tcl +++ b/regression.tcl @@ -84,6 +84,8 @@ evaluateRegressionLevel $defaultStep $regressionLevels if {![file exists $::poc::localConfigurationPath] || $::regression::level == -1} { WriteLocalConfiguration +} else { + puts "${::poc::putsPrefix}Skipping local configuration file generation." } puts "========================================" diff --git a/tools/poc.tcl b/tools/poc.tcl index 11cc366e5..79794ffec 100644 --- a/tools/poc.tcl +++ b/tools/poc.tcl @@ -1,5 +1,6 @@ namespace eval ::poc { - variable putsPrefix "\[PoC\] " + variable putsPrefix "\[PoC\] " + variable putsPrefixNs "\[PoC\] " proc getEnv {var {default ""}} { if {[info exists ::env($var)]} { return $::env($var) @@ -230,10 +231,10 @@ ${::poc::putsPrefix}====================================== # New procedures for OSVVM's *.pro files proc disabled {args} { - puts "${::poc::putsPrefix}Disabled from analysis: $args" + puts "${::poc::putsPrefixNs}Disabled from analysis: $args" } proc duplicate {args} { - puts "${::poc::putsPrefix}Duplicate file: $args" + puts "${::poc::putsPrefixNs}Duplicate file: $args" } namespace export exitScript From 8dd6f940c93d5c4cbef055f5a706ffd7126fb368 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 20 Jun 2026 11:08:01 +0200 Subject: [PATCH 18/18] Improve GitLab and GitHub pipelines. --- .github/workflows/Pipeline.yml | 4 +- .github/workflows/Simulate.yml | 221 ++++++++++++++++++++++++++------- .gitlab-ci.yml | 13 +- tools/poc.tcl | 2 + 4 files changed, 186 insertions(+), 54 deletions(-) diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml index 89ca653b3..cbc5f313b 100644 --- a/.github/workflows/Pipeline.yml +++ b/.github/workflows/Pipeline.yml @@ -24,7 +24,7 @@ jobs: fail-fast: false matrix: include: - - {ubuntu-version: 'ubuntu-24.04', simulator: 'nvc', backend: '', version: 'latest', can-fail: false} + - {ubuntu-version: 'ubuntu-26.04', simulator: 'nvc', backend: '', version: 'latest', can-fail: false} - {ubuntu-version: 'ubuntu-26.04', simulator: 'ghdl', backend: 'mcode', version: 'nightly', can-fail: false} - {ubuntu-version: 'ubuntu-26.04', simulator: 'ghdl', backend: 'llvm', version: 'nightly', can-fail: false} with: @@ -41,7 +41,7 @@ jobs: - Simulate # if: success() || failure() with: - unittest_artifacts_pattern: 'PoC-Report-XML-*' + unittest_artifacts_pattern: 'SimPoC-Report-XML-*' testsuite-summary-name: 'The PoC Library' merge-input-dialect: 'Any-JUnit' merged_junit_filename: 'unittest.xml' diff --git a/.github/workflows/Simulate.yml b/.github/workflows/Simulate.yml index e4ed538df..368c6146f 100644 --- a/.github/workflows/Simulate.yml +++ b/.github/workflows/Simulate.yml @@ -35,12 +35,17 @@ on: osvvm-artifact-prefix: description: 'Prefix of OSVVM artifacts.' required: false - default: 'OSVVM' + default: 'BuildOSVVM' type: string poc-artifact-prefix: description: 'Prefix of PoC artifacts.' required: false - default: 'PoC' + default: 'BuildPoC' + type: string + sim-artifact-prefix: + description: 'Prefix of PoC artifacts.' + required: false + default: 'SimPoC' type: string jobs: @@ -51,15 +56,19 @@ jobs: tempDirectory: ${{ steps.Variables.outputs.tempDirectory }} startScript: ${{ steps.Variables.outputs.startScript }} artifactSuffix: ${{ steps.Variables.outputs.artifactSuffix }} + osvvmGenerated: ${{ steps.ArtifactNames.outputs.osvvmGenerated }} osvvmLibraries: ${{ steps.ArtifactNames.outputs.osvvmLibraries }} osvvmReportHTML: ${{ steps.ArtifactNames.outputs.osvvmReportHTML }} osvvmReportYAML: ${{ steps.ArtifactNames.outputs.osvvmReportYAML }} osvvmReportXML: ${{ steps.ArtifactNames.outputs.osvvmReportXML }} - osvvmGenerated: ${{ steps.ArtifactNames.outputs.osvvmGenerated }} + pocGenerated: ${{ steps.ArtifactNames.outputs.pocGenerated }} pocLibraries: ${{ steps.ArtifactNames.outputs.pocLibraries }} pocReportHTML: ${{ steps.ArtifactNames.outputs.pocReportHTML }} pocReportYAML: ${{ steps.ArtifactNames.outputs.pocReportYAML }} pocReportXML: ${{ steps.ArtifactNames.outputs.pocReportXML }} + simReportHTML: ${{ steps.ArtifactNames.outputs.simReportHTML }} + simReportYAML: ${{ steps.ArtifactNames.outputs.simReportYAML }} + simReportXML: ${{ steps.ArtifactNames.outputs.simReportXML }} steps: - name: 🖉 Compute variables @@ -87,15 +96,19 @@ jobs: id: ArtifactNames run: | tee --append "${GITHUB_OUTPUT}" <