From 708fbaecf0839b18498da53da72728d3df2508a6 Mon Sep 17 00:00:00 2001 From: Codex Date: Fri, 11 Sep 2026 09:40:36 -0700 Subject: [PATCH 1/2] docs: present the autonomous target SoC on the homepage OpenChip-Provenance: v1 Agent-Label: root Agent-Role: orchestrator Agent-Provider: OpenAI Agent-Client: Codex Agent-Backend: UNKNOWN Requested-Model: UNKNOWN Requested-Effort: UNKNOWN Observed-Identity: UNKNOWN Runtime-Attestation: none Runtime-Evidence: UNKNOWN Platform-Host: github.com Platform-Account-Login: codex Platform-Account-ID: 267193182 Platform-Account-Type: User Platform-Action: commit-author-identity Platform-Evidence: https://api.github.com/repos/jonnipm-web/ai-social-copilot/commits/184e0599a6d5f2c50776a998bcd9a8bf5fa41ab1 --- README.md | 36 ++++---- docs/images/chip-architecture.svg | 131 +++++++++++++++--------------- 2 files changed, 88 insertions(+), 79 deletions(-) diff --git a/README.md b/README.md index b038752..b1c74ea 100644 --- a/README.md +++ b/README.md @@ -1,20 +1,26 @@ # OpenChip OpenChip is an open framework for building silicon with collaborating engineering -agents. Our current chip direction brings **CoralNPU** into a system for complete -LLM workloads. +agents. Our chip target is **autonomous execution of a complete small language +model**, built with open hardware and carried through to working silicon. -## Chip architecture +## Target chip architecture -![OpenChip architecture: the selected CoralNPU core contains RV32/RVV execution and 1 MiB each of instruction and data TCM. Native AXI connects it to host-control and external-memory simulation adapters. A separate band lists the SoC integration work ahead.](docs/images/chip-architecture.svg) +![OpenChip target SoC: CoralNPU executes complete stories260K in FP32 at a 40-token runtime context and performs tokenization. Boot ROM, working SRAM, an AXI fabric, a Flash controller, UART, system control and manufacturing-test functions form the chip. External NOR Flash stores firmware and model weights. The chip boots and runs autonomously; a serial terminal supplies text input and receives output.](docs/images/chip-architecture.svg) -The selected core combines **RV32 + RVV** execution with **1 MiB instruction TCM** -and **1 MiB data TCM**. Host control and external memory are simulation adapters -today; the production SoC interfaces remain to be defined and qualified. +The target chip boots from its own ROM, checks firmware and model images in +external Flash, and runs the complete prefill and decode loop on CoralNPU. +Tokenization, model execution and text generation run on the chip. A serial +terminal provides input and output. Automatic boot and fixture execution work +without a connected host. -[Native IP](hw/ip/coralnpu/README.md) · -[Integration contract](docs/spec/coralnpu_external_memory.md) · -[Complete tiny-LM workload](workloads/coralnpu_llm/README.md) (draft) +**First-silicon workload:** the complete stories260K model in FP32, with a +40-token runtime context. This architecture is a design target; implementation +and physical qualification are tracked separately from this system view. + +[Target contract](docs/spec/coralnpu_soc.md) · +[Architecture decision](docs/adr/0006-autonomous-small-model-soc.md) · +[Native IP](hw/ip/coralnpu/README.md) Architecture, RTL, verification, software and physical design have separate owners. An orchestrator manages the goal and dependencies; specialists deliver @@ -74,10 +80,12 @@ and experiment receipts stay in the approved local store, outside public history ## Direction and documentation The [CoralNPU native IP entry](hw/ip/coralnpu/README.md) now provides pinned source -acquisition, native model generation and runtime tooling. The next engineering -steps are complete target LLM execution and SoC integration; the -[full-model contract](docs/spec/coralnpu_llm.md) remains a draft. The smaller -tinyNPU stays a fast framework regression. See the [roadmap](docs/ROADMAP.md). +acquisition, native model generation and runtime tooling. The complete-model +[engineering contract](docs/spec/coralnpu_llm.md) remains a draft and supplies +workload evidence for the target SoC. Autonomous boot, real memory/peripheral +integration and physical qualification follow their own reviewed contracts. +The smaller tinyNPU stays a fast framework regression. See the +[roadmap](docs/ROADMAP.md). - [Constitution and ownership](AGENTS.md): startup, independent roles and branch delivery. - [Silicon lifecycle](docs/SILICON_LIFECYCLE.md): incremental, scoped signoff from feasibility through production validation. diff --git a/docs/images/chip-architecture.svg b/docs/images/chip-architecture.svg index e3b7c37..51fc7fe 100644 --- a/docs/images/chip-architecture.svg +++ b/docs/images/chip-architecture.svg @@ -1,66 +1,67 @@ - - OpenChip: CoralNPU integration architecture - The selected imported RvvCoreMiniHighmemAxi contains RV32 and RVV execution with a 128-bit vector length, 1 MiB instruction TCM and 1 MiB data TCM. A host-control simulation adapter connects to its native AXI subordinate port. Its native AXI manager port connects to a behavioral external-memory responder for code and data. The separate dashed band lists future SoC requirements, not selected hardware: boot and host interface, system interconnect, external memory interface, clock, reset and interrupts. - - - - - + +OpenChip target SoC proposal + A standalone chip running the complete stories260K FP32 model at a 40-token runtime context. The autonomous boot sequencer has a separate path to the core subordinate CSR and reset controls. Inside the chip are CoralNPU, boot ROM, working SRAM, AXI fabric, flash controller, UART, system control, debug and test. External NOR flash stores firmware and the complete model. A serial terminal provides input and output. Boot proceeds from reset to ROM to checked flash firmware and inference without a host loader. Proposed target architecture, pending independent review; implementation progress is separate. + + + + + - - - OPENCHIP / SYSTEM VIEW - CoralNPU at the core. - Current integration baseline - - - - CoralNPU - - Imported IP - RvvCoreMiniHighmemAxi - - - RV32 + RVV - 128-bit vector length - - - Instruction TCM - 1 MiB - - Data TCM - 1 MiB - - - - Host control - Simulation adapter - Load · configure · start - - AXI - subordinate - control / status - - - External - memory model - Behavioral responder - - AXI - manager - code + data - - - - Next: SoC integration - Architecture to define and qualify - Boot & host interface - System interconnect - Memory interface - Clock · reset · interrupts - + +OPENCHIP / TARGET SOC +A complete model. An autonomous chip. +Complete stories260K · FP32 · 40-token runtime context + +ON CHIP + + CoralNPU + RV32 + RVV · control and inference + 8 KiB ITCM · 32 KiB DTCM + Model execution + tokenization + + Boot ROM + 16 KiB + Check · boot · recover + + Working SRAM + 64 KiB + KV · input · output · status + + + + + Native AXI fabric + peripheral bridge + + + + + System control + Timer · IRQ · watchdog + + UART + GPIO + Prompt in · generated text out + + Flash controller + Memory-mapped QSPI reads + + Clock / reset / autonomous boot + Boot sequencer → core subordinate CSR / reset + + + Test: JTAG / scan · SRAM BIST +OFF CHIP / BOARD +Reference clock + Reset · power + Test / debug pins + + NOR Flash + 4 MiB + Firmware + full model + + + Serial terminal + Text input / output + +Power on → boot ROM → validated firmware → complete inference → text output +Target architecture · implementation and physical qualification are tracked separately. + \ No newline at end of file From 4f41f1a929848c59cd61e8bcbfe7f55a3a84f6aa Mon Sep 17 00:00:00 2001 From: Codex Date: Fri, 11 Sep 2026 09:44:00 -0700 Subject: [PATCH 2/2] docs: align accessible text with the target architecture OpenChip-Provenance: v1 Agent-Label: root Agent-Role: orchestrator Agent-Provider: OpenAI Agent-Client: Codex Agent-Backend: UNKNOWN Requested-Model: UNKNOWN Requested-Effort: UNKNOWN Observed-Identity: UNKNOWN Runtime-Attestation: none Runtime-Evidence: UNKNOWN Platform-Host: github.com Platform-Account-Login: codex Platform-Account-ID: 267193182 Platform-Account-Type: User Platform-Action: commit-author-identity Platform-Evidence: https://api.github.com/repos/jonnipm-web/ai-social-copilot/commits/184e0599a6d5f2c50776a998bcd9a8bf5fa41ab1 --- docs/images/chip-architecture.svg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/images/chip-architecture.svg b/docs/images/chip-architecture.svg index 51fc7fe..33f952a 100644 --- a/docs/images/chip-architecture.svg +++ b/docs/images/chip-architecture.svg @@ -1,6 +1,6 @@ -OpenChip target SoC proposal - A standalone chip running the complete stories260K FP32 model at a 40-token runtime context. The autonomous boot sequencer has a separate path to the core subordinate CSR and reset controls. Inside the chip are CoralNPU, boot ROM, working SRAM, AXI fabric, flash controller, UART, system control, debug and test. External NOR flash stores firmware and the complete model. A serial terminal provides input and output. Boot proceeds from reset to ROM to checked flash firmware and inference without a host loader. Proposed target architecture, pending independent review; implementation progress is separate. +OpenChip target SoC architecture + A standalone chip running the complete stories260K FP32 model at a 40-token runtime context. The autonomous boot sequencer has a separate path to the core subordinate CSR and reset controls. Inside the chip are CoralNPU, boot ROM, working SRAM, AXI fabric, flash controller, UART, system control, debug and test. External NOR flash stores firmware and the complete model. A serial terminal provides input and output. Boot proceeds from reset to ROM to checked flash firmware and inference without a host loader. Logical target architecture; implementation and physical qualification are tracked separately.