From 3d1630b4a148ed40d6eb21691e7f5794aea7b944 Mon Sep 17 00:00:00 2001 From: David Anderson Date: Sun, 16 Aug 2026 11:55:36 -0700 Subject: [PATCH 1/2] Add TryFrom bounds for all integer primitive types to SimdIntElement Signed-off-by: David Anderson --- CHANGELOG.md | 1 + fearless_simd/src/traits.rs | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 923f04e0..f6c1e083 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,6 +16,7 @@ You can find its changes [documented below](#070-2026-08-11). - Added lane-wise `count_ones` and `count_zeros` operations for all integer vector types and backends. - Added `mul_add_precise` and `mul_sub_precise` for floating-point vectors. They guarantee the infinite-precision product-plus-add rounded once, including on SIMD levels without hardware fused multiply-add instructions. They are not susceptible to the [bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library, `std::simd` and musl libc that causes incorrect rounding for subnormal results. SSE4.2 gets SIMD emulation of these operations for better performance. ([#323][], [#324][] by [@Shnatsel][]) - Documented the storage representation of the SIMD vector types. The documented representation will not change without a semver major version change. +- Added `TryFrom` bounds to `SimdIntElement`, allowing attempted conversion from all primitive integer types. ### Changed diff --git a/fearless_simd/src/traits.rs b/fearless_simd/src/traits.rs index 49d90a94..d94deb4c 100644 --- a/fearless_simd/src/traits.rs +++ b/fearless_simd/src/traits.rs @@ -6,6 +6,7 @@ reason = "TODO: https://github.com/linebender/fearless_simd/issues/40" )] use crate::{Simd, SimdBase, seal::Seal}; +use core::error::Error; use core::fmt::{Binary, Debug, Display, LowerExp, UpperExp}; use core::iter::{Product, Sum}; use core::ops::{ @@ -219,6 +220,18 @@ pub trait SimdIntElement: + BitOrAssign + BitXor + BitXorAssign + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + for<'a> Shl<&'a usize, Output = Self> + for<'a> ShlAssign<&'a usize> + for<'a> Shr<&'a usize, Output = Self> From fc72a3d42d7bddfee9b4a4623ade0f8c7cc7e543 Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Wed, 26 Aug 2026 22:39:05 +0100 Subject: [PATCH 2/2] More succinct bounds: Eq implies PartialEq, Copy implies Clone --- fearless_simd/src/traits.rs | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/fearless_simd/src/traits.rs b/fearless_simd/src/traits.rs index d94deb4c..96da83ec 100644 --- a/fearless_simd/src/traits.rs +++ b/fearless_simd/src/traits.rs @@ -220,18 +220,18 @@ pub trait SimdIntElement: + BitOrAssign + BitXor + BitXorAssign - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom - + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + + TryFrom + for<'a> Shl<&'a usize, Output = Self> + for<'a> ShlAssign<&'a usize> + for<'a> Shr<&'a usize, Output = Self>