From aacab75db52279abb38070bfe6f35cc14967f88b Mon Sep 17 00:00:00 2001 From: Jimmy Ho Date: Tue, 19 Aug 2025 15:13:18 +0800 Subject: [PATCH] riscv: fix using wrong load type thread_info.cpu field is 32 bits wide, but is accessed using an XLEN-bit load, which might be 64bit load, fix it Changes in v3: - replace space with tab to keep it aligned with code block - Add "Fixes" tag Changes in v2: - add a comment to explain why use lw instead of REG_L. - correct commit message Fixes: 503638e0babf3 ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") Signed-off-by: Jimmy Ho Signed-off-by: Linux RISC-V bot --- arch/riscv/kernel/entry.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 3a0ec6fd595691..492ae936dccdda 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -45,8 +45,10 @@ * Computes: * a0 = &new_vmalloc[BIT_WORD(cpu)] * a1 = BIT_MASK(cpu) + * + * using lw instead of REG_L is because the thread_info.cpu field is 32 bits wide */ - REG_L a2, TASK_TI_CPU(tp) + lw a2, TASK_TI_CPU(tp) /* * Compute the new_vmalloc element position: * (cpu / 64) * 8 = (cpu >> 6) << 3