Feature request : Generation of SystemVerilog header file (.svh)

[martin-tanguay]

Hi,

It would be a nice feature to be able to generate a SystemVerilog header file (.svh) when generating a regblock. That would be particularly useful for testbenches.

Let me know.

Martin

[amykyta3]

This would be a better fit as a PeakRDL tool separate from the regblock generator. Looking at the community page, it doesn't look like anyone implemented such a tool yet.

Should be pretty easy to implement such a code generator if you're interested. Some relevant docs that may help:

• Implementing a PeakRDL exporter plugin
• Example: iterating over a compiled design
• Other example: Implementation of the PeakRDL dump command
• SystemRDL gotchyas for tool developers

I'd be happy to add it to the community page if someone were to implement such a tool!

[martin-tanguay]

Thanks for the quick reply.

Just found this plugin : https://github.com/muneebullashariff/PeakRDL-svh

I haven't tried it yet. I'm fairly new with how to use an exporter. I'll read the links you sent me.

[amykyta3]

Ah yes I forgot about that one. Generally I only add community extensions if they are published to PyPi with controlled versioning. Also, it looks like it only implements the exporter as a Python API, and does not provide a plugin to the PeakRDL command-line. @muneebullashariff would you be open to enhancing your tool to make it more accessible?

[martin-tanguay]

@muneebullashariff that would be really great if that's possible.

[fischeti]

I think the PeakRDL-rawheader plugin would help :) We implemented it for the same reason i.e. dumping addresses that can be reused in a SystemVerilog testbench.

[martin-tanguay]

Thanks for the heads up @fischeti, I'll try it out. Martin