From 1767dff462a70fa3e89eddf2c609de87d1c12133 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Wed, 5 Aug 2026 16:28:26 +0530 Subject: [PATCH] arm64: dts: qcom: nord: Add UART17 hardware flow-control pins Add CTS/RTS pinctrl configuration for UART17 and include it in the default pinctrl state. Configure GPIO150 and GPIO151 for UART17 hardware flow-control operation. Signed-off-by: Jyothi Kumar Seerapu --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 010080e8d04fb..352fa1a08d065 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -1740,6 +1740,13 @@ bias-disable; }; + qup_uart17_cts_rts: qup-uart17-cts-rts-state { + pins = "gpio150", "gpio151"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-down; + }; + qup_uart18_default: qup-uart18-default-state { pins = "gpio143", "gpio144"; function = "qup2_se4"; @@ -1962,7 +1969,7 @@ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; - pinctrl-0 = <&qup_uart17_default>; + pinctrl-0 = <&qup_uart17_default>, <&qup_uart17_cts_rts>; pinctrl-names = "default"; };