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Fix Log precision and Pow returning 1 for a zero base #10

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Merged
Auburn merged 1 commit into from
Oct 14, 2026
Merged

Fix Log precision and Pow returning 1 for a zero base #10

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5 changes: 3 additions & 2 deletions include/FastSIMD/ToolSet/Generic/Functions.h
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Original file line number Diff line number Diff line change
Expand Up @@ -634,7 +634,7 @@ namespace FS

RegisterF xx = value * value;
y *= xx;
y *= e * RegisterF( -2.12194440e-4f );
y += e * RegisterF( -2.12194440e-4f );
y -= xx * RegisterF( 0.5f );

value += y;
Expand All @@ -648,12 +648,13 @@ namespace FS
}
}

// value <= 0 returns 0, matching 0^pow for pow > 0
template<typename T, std::size_t N, FastSIMD::FeatureSet SIMD>
FS_FORCEINLINE Register<T, N, SIMD> Pow( const Register<T, N, SIMD>& value, const Register<T, N, SIMD>& pow )
{
if constexpr( IsNativeV<Register<T, N, SIMD>> )
{
return Exp( pow * Log( value ) );
return Masked( value > Register<T, N, SIMD>( 0 ), Exp( pow * Log( value ) ) );
}
else
{
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8 changes: 8 additions & 0 deletions tests/test.inl
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Expand Up @@ -454,6 +454,14 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
b = FS::Min( FS::Max( b, TestRegf32( -8.0f ) ), TestRegf32( 8.0f ) );
return FS::Pow( a, b );
} ).relaxedAccuracy = 16384;
RegisterTest( tests, "f32 pow zero base", []( TestRegf32 a, TestRegf32 b ) {
// Negative inputs become a zero base, ranges avoid Exp overflow
auto zero = a < TestRegf32( 0.0f );
a = FS::Min( FS::Max( a, TestRegf32( 1.e-4f ) ), TestRegf32( 1.e+4f ) );
a = FS::Select( zero, TestRegf32( 0.0f ), a );
b = FS::Min( FS::Max( FS::Abs( b ), TestRegf32( 0.1f ) ), TestRegf32( 8.0f ) );
return FS::Pow( a, b );
} ).relaxedAccuracy = 16384;

RegisterTest( tests, "i32 convert to f32", []( TestRegi32 a ) { return FS::Convert<float>( a ); } );
RegisterTest( tests, "f32 convert to i32", []( TestRegf32 a ) { return FS::Convert<int32_t>( FS::Min( FS::Max( a, TestRegf32( -2147483647 - 1 ) ), TestRegf32( 2147483520 ) ) ); } );
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