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Jana-Frangi/README.md

Hi, I'm Jana 👋

I'm a Computer & Communications Engineering student at the American University of Beirut (AUB), currently completing an exchange semester at Politecnico di Torino.

I'm interested in the hardware behind modern computing systems, particularly digital design, electronics, computer architecture, integrated circuits, and hardware for AI systems.

🔧 Technical Interests

  • Digital & Analog IC Design
  • Computer Architecture
  • FPGA & RTL Design
  • CMOS Circuit Design
  • Embedded & Computer Systems
  • AI Hardware & Hardware–Software Co-Design

🛠️ Technologies & Tools

Hardware & Design: Verilog • RISC-V • Xilinx Vivado • LTspice • GF180MCU
Programming: Python • C++ • Assembly
Systems: TCP/IP • Socket Programming • Multithreading • Computer Networking

📌 Selected Projects

🚧 Currently organizing and documenting my engineering projects.

Projects in RISC-V architecture, CMOS integrated circuit design, FPGA development, networking, and computer systems will be added here.

🌍 Currently

📍 Exchange Student — Politecnico di Torino, Italy
🎓 B.E. Computer & Communications Engineering — American University of Beirut

🔗 Connect

LinkedIn

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  1. rv32ic-fetch-stage rv32ic-fetch-stage Public

    Verilog implementation of an RV32IC instruction fetch stage with RISC-V compressed instruction decompression and dynamic PC+2/PC+4 control.

    Verilog