Add explicit CPU-state AdamW with scoped CUDA resume evidence

[CompleteDotTech]

Change

Add explicit experimental cpu_state_streaming_v1 AdamW for CUDA FP32 parameters, with persistent CPU moments, versioned resume identity, validation before restore, and a required persistent-state byte ceiling. Default and fused backend behavior and historical configuration hashes are preserved. Release restored checkpoint payloads before optimization.

Validation

• Final full CPU suite: 875 passed, 62 explicit skips in 81.07 seconds (CUDA/SDK/platform prerequisite skips remain explicit).
• Actual integrated CUDA primitives: 8 passed, zero failed/skipped.
• Tiny synthetic rank0: all 8 FP32/BF16 uninterrupted/save/exit/fresh-resume/reload comparison phases passed.
• Tiny synthetic LoRA rank4 with activation checkpointing: all 8 corresponding phases passed; reused the prior primitive proof, 26 frozen states unchanged and LoRA/head updates observed.
• Full model, optimizer, RNG and recursive resume-state comparisons were exact. Live CPU optimizer states remained CPU-resident and within their declared byte ceiling.
• Compile, indexed source integrity, preserved 45-feature matrix, critical lint, lock/schema, 24-configuration CPU audit and local resume/calibration gates passed.

Portable hash-bound receipts preserve runtime source b5d8299 and measured GPU allocation. Local raw artifacts and model weights are excluded.

Remaining acceptance

These are synthetic fixture results. Actual pretrained fullweight step/save/exit/resume/reload and captured-gradient stock optimizer oracle remain pending under the unchanged 16 GiB available-host admission requirement. The byte ceiling bounds persistent optimizer tensors, not total host RAM. No native derivative, exact-limit context, representative quality or Jev advantage is established. Issue #3 remains open; Overwatch stays archived per user instruction.

Refs #3