This project is based on nand2mario's SNESTang and is a work in progress to bring it to the MiSTle framework. It retains the improvements from nand2mario's project while adapting the core and its I/O system for MiSTle boards.
There is currently an IcePi-Zero build with USB HID support. It also works with the MiSTle IcePi carrier board, which offers broader USB compatibility with IcePi-Zero. Other board configurations are present in the source tree, but the MiSTle port is still in progress.
This core can be built to support the MiSTle framework and its FPGA Companion MCU when run on the MiSTle GW5A-25K or the Tang Nano 20k. In this case the SNESTangs own On-Screen-Display is being disabled and the MiSTle OSD is being used instead. This can be invoked as usual via F12 if a keyboard is connected or by pressing Select + Start on the first gamepad.
Due to space constraints only DSP1 is supported on the Nano20k. This is the majority of DSP based games incl. Mario Kart. The MiSTle GW5A-25K supports all DSP variants.
The USB HID controllers run in FPGA gateware; IcePi-Zero has no dedicated USB controller chip for them. Some USB HID devices may therefore be incompatible. Each port supports one device, so USB hubs and composite devices such as combined keyboard/mouse units may not work. Low-speed and full-speed USB 2.0 HID devices are the intended devices. This limitation is also described in the IcePi-Zero Minimig USB support notes.
On IcePi-Zero, the first player uses the second USB port, the one closer to the PCB edge, for easier physical access. The other USB port is for the second player.
Controllers without dedicated Start and Select buttons can use these chords:
| Hold | Press | SNES button |
|---|---|---|
| X + Y | A | Start |
| X + Y | B | Select |
The mapping applies to both players and all controller inputs. Dedicated Start and Select buttons still work. While either chord is held, its face buttons are not sent to the game; directions and shoulder buttons still work.
Press Select + Right to open the on-screen display (OSD).
At a high level, the work since fbd8217 includes:
- Changed the I/O soft CPU to SERV in its 4-bit QERV mode to reduce FPGA resource use. The I/O system was also refactored and gained streamed ROM loading.
- Updated the SNES core modules from the upstream MiSTer SNES core, keeping the migrated VHDL sources where practical. The 65C816 CPU uses its Verilog implementation because the VHDL version used too many LUTs.
- Migrated all of nand2mario's improvements, including the existing SNESTang integration and features.
- Added MiSTle board support and adapted the build, memory, HDMI, and audio paths for Gowin and Lattice ECP5 targets. Simulation was restored for the mixed Verilog/VHDL design.
- Added an IcePi-Zero project and connected the USB HID host to its USB ports.
First, get firmware.bin from the SnesTang firmware repository and flash it at offset 0x500000:
openFPGALoader -b icepi-zero --write-flash --offset 0x500000 firmware.binThen flash the IcePi-Zero core bitstream:
openFPGALoader -b icepi-zero --write-flash path/to/core.bitReplace path/to/core.bit with the path to the built bitstream. Flash the firmware before using the core.
Since these use the MiSTle framework and don't use an FPGA embedded MCU, no firmware needs to be flashed. Just the core bitstream itself has to be installed:
openFPGALoader path/to/core.fsThe design notes describe the original SNESTang architecture. The Verilator harness provides simulation support.
SNESTang was created by nand2mario as part of TangCore. Its SNES core derives from SNES_FPGA by Sergiy Dvodnenko (srg320) and gyurco and the MiSTer SNES core. HDMI support uses hdl-util/hdmi by Sameer Puri.