Section: Appendix F.3 (Dynamic Array Layout), F.4 (String Memory Layout)
Problem:
Both headers omit the 4-byte padding field present on 64-bit targets. The actual RTL structures (TDynArrayRec / StrRec in System.pas) have a _Padding: LongInt field before the documented fields under {$IFDEF CPUX64}, added specifically to keep the payload 16-byte aligned. As written, the documented Win64 header sizes don't match the actual 16-byte-aligned layout.
Suggested fix:
Add the conditional padding field to both diagrams for 64-bit platforms, and note its purpose (16-byte payload alignment).
Section: Appendix F.3 (Dynamic Array Layout), F.4 (String Memory Layout)
Problem:
Both headers omit the 4-byte padding field present on 64-bit targets. The actual RTL structures (
TDynArrayRec/StrRecinSystem.pas) have a_Padding: LongIntfield before the documented fields under{$IFDEF CPUX64}, added specifically to keep the payload 16-byte aligned. As written, the documented Win64 header sizes don't match the actual 16-byte-aligned layout.Suggested fix:
Add the conditional padding field to both diagrams for 64-bit platforms, and note its purpose (16-byte payload alignment).