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LatencyLab

A DPDK-Based P4 Pipeline Latency Measurement Framework for FPGA SmartNICs

Overview

LatencyLab measures per-packet processing latency of P4 pipelines running on FPGA SmartNICs, using two independent techniques: a TSC-based differential estimator (corrected via null-bitstream calibration) and an independent hardware-clock validation, obtained by kernel-free reflection of every probe packet to a ConnectX-5 NIC. Four P4 programs — Forward, FiveTuple, RemoveHeader, Checksum — were measured across 5 sessions x 10 runs x 20,000 packets each, on the Open Cloud Testbed (OCT) using Xilinx Alveo U280 cards running Open-NIC-Shell.

Repository layout

Path Contents
p4/ Reference to the P4 source (maintained in a separate repo)
bitstreams/ Compiled FPGA bitstreams, .mcs (Git LFS)
receiver/ DPDK measurement engine + automation — runs on the FPGA host
sender/ Traffic generation + hardware-clock capture/analysis — sender
emulator/ Vendor worst-case latency model (VitisNetP4 calculated latency + insertion penalty)
data/ Raw and processed measurement data (tsc/, pcap/, silicon/)

Testbed

Two nodes on the Open Cloud Testbed (OCT), using the CloudLab profile: https://www.cloudlab.us/show-profile.php?uuid=f9577a58-4186-11ee-9f39-e4434b2381fc

  • Receiver node — hosts the AU280 FPGA SmartNIC; runs the DPDK receiver/reflector (see receiver/README.md).
  • Sender node — sends probe traffic via tcpreplay and independently captures reflected packets with hardware timestamps (see sender/README.md).

Reproducing the measurements

  1. Get the P4 source and bitstreams — see p4/README.md and bitstreams/README.md.
  2. Run a measurement campaign — see receiver/README.md and sender/README.md. The two sides run in coordination: the sender waits for a per-session ready signal from the receiver before capturing. Note that some hardware-specific values (PCIe addresses, interface names, MAC addresses) are testbed-specific and must be adjusted on new hardware — see the "Configuration required" section in receiver/README.md.
  3. Resulting data lands under data/ — see data/README.md for the exact layout and file formats.

Citation

TODO: add the paper citation once published.

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A DPDK-Based P4 Pipeline Latency Measurement Framework for FPGA SmartNICs

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