Set CPU Frequency #57

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1. SzigetiJ

   added this to the 1.0 milestone on Jul 26, 2026
2. SzigetiJ

   self-assigned this

   on Jul 26, 2026
3. SzigetiJ

   added

   enhancementNew feature or requestNew feature or request

   on Jul 26, 2026
4. SzigetiJ commented on Jul 26, 2026

   

   SzigetiJ

   on Jul 26, 2026

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   Setting 160MHz -> 80MHz works by default:

   // CPU_CPUPERIOD_SEL. 0: x/4, 1: x/2, 2: x/3 (480MHz PLL_CLK).
   #define CPU_CPUPERIOD_SEL 0
   dport_regs()->CPU_PER_CONF = (CPU_CPUPERIOD_SEL << 0);
5. SzigetiJ commented on Jul 29, 2026

   

   SzigetiJ

   on Jul 29, 2026

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   Found the corresponding code in esp-idf:

   void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)

   To set CPU freq to 240MHz, we also have to adjust the CPU voltage:

   REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);

   The bit values come from consts and efuse parameter

   #define RTC_CNTL_DBIAS_HP_VOLT         (RTC_CNTL_DBIAS_1V25 - efuse_ll_get_vol_level_hp_inv())

   The esp-idf procedure also does the followings:

   • switch to XTAL;
   • disable BBPLL;
   • enable BBPLL;
   • configure BBPLL;
   • and finally switch back to PLL with the new freq.
6. SzigetiJ commented on Jul 30, 2026

   

   SzigetiJ

   on Jul 30, 2026

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   This is kind of WIP report.

   I managed to switch from PLL to XTL as cpu clk src, but switching from XTL to PLL(240MHz) or from PLL(160MHz) to PLL(240MHz) is not resolved yet. The digital voltage regulator output level settings seem to have effect (there is a change in flowing current (and power consumption)), so the problem lies somewhere else.

   Anyway, the lessons already learned:

   • With XTL_CLK (40MHz) the flowing current drops from ~ 0.040A to ~ 0.025A, which is a significant change. We should consider introducing a so-called rest_state or whatever, when the prog_cycle_xxx() tasks are already done and there is no interrupt expected to happen. And during this rest_state we can switch to XTL_CLK. Of course, there are many things to do, e.g., measure the time delay caused by switching, check clock accuracy, etc.
   • With XTL_CLK the APB_CLK frequency drops (from 80MHz) to 40MHz (or even lower if we shrink the CPU freq by increasing the SYSCON_PRE_DIV_CNT value). Currently the 80MHz is a hardwired value (#define-d) with all its derivatives (including the widely used MS2TICKS(X) macro). By introducing this clock swich, APB_FREQ_HZ becomes a variable (or at least can have any value of a predefined set, e.g., 80, 40, 20, 10, 5, 2, 1 MHz), so this change must be elaborated deeper.
7. SzigetiJ commented on Aug 4, 2026

   

   SzigetiJ

   on Aug 4, 2026

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   Done. See #60

   Note, using XTL_CLK, at CPU frequency of 4 MHz, UART0 does not work as expected. With higher CPU frequencies, UART0 is fine.
8. SzigetiJ

   closed this as completedon Aug 4, 2026