Process meta information

[el3ctrician]

Hello,
I am working on a VHDL schematic viewer that lets you analyze and visualize a VHDL entity and see all connection to instances, proceesses etc. For that i wanted to figure out what are the "inputs" and "outputs" of a process as inputs defined as any signal that's "read" from withing the process and output is any signal that's driven by the process and for the following snippet code in vhdl

 process (clk)
    begin
        if rising_edge(clk) then
            if d = '0' then
                d <= g or s;
            else
                d <= g and s;
            end if;

        end if;
    end process;

Since i am using pyGHDL as a backend (i really want to move from it since i don't want/need GHDL) and with the help of AI i came up with the following code that parsers IIR nodes :

   def __get_iir_name(self, iir) -> str:
      ident = nodes.Get_Identifier(iir)
      return name_table.Get_Name_Ptr(ident)

  def __collect_names_from_iir(self, iir, names: set, visited=None):
      if visited is None:
          visited = set()
      if iir is None or iir == 0 or iir in visited:
          return
      visited.add(iir)

      kind = nodes.Get_Kind(iir)

      if kind == Iir_Kind.Simple_Name:
          names.add(self.__get_iir_name(iir))
          return

      if kind == Iir_Kind.Selected_Name:
          self.__collect_names_from_iir(nodes.Get_Prefix(iir), names, visited)
          return

      if kind in (Iir_Kind.Function_Call, Iir_Kind.Procedure_Call_Statement):
          assoc = nodes.Get_Parameter_Association_Chain(iir)
          while assoc != 0:
              actual = nodes.Get_Actual(assoc)
              self.__collect_names_from_iir(actual, names, visited)
              assoc = nodes.Get_Chain(assoc)
          return

      if kind in (
          Iir_Kind.And_Operator,
          Iir_Kind.Or_Operator,
          Iir_Kind.Nand_Operator,
          Iir_Kind.Nor_Operator,
          Iir_Kind.Xor_Operator,
          Iir_Kind.Xnor_Operator,
          Iir_Kind.Equality_Operator,
          Iir_Kind.Inequality_Operator,
          Iir_Kind.Less_Than_Operator,
          Iir_Kind.Greater_Than_Operator,
          Iir_Kind.Less_Than_Or_Equal_Operator,
          Iir_Kind.Greater_Than_Or_Equal_Operator,
          Iir_Kind.Addition_Operator,
          Iir_Kind.Substraction_Operator,
          Iir_Kind.Multiplication_Operator,
          Iir_Kind.Division_Operator,
          Iir_Kind.Concatenation_Operator,
      ):
          self.__collect_names_from_iir(nodes.Get_Left(iir), names, visited)
          self.__collect_names_from_iir(nodes.Get_Right(iir), names, visited)
          return

      if kind in (
          Iir_Kind.Not_Operator,
          Iir_Kind.Negation_Operator,
          Iir_Kind.Identity_Operator,
      ):
          self.__collect_names_from_iir(nodes.Get_Operand(iir), names, visited)
          return

      if kind in (Iir_Kind.Type_Conversion, Iir_Kind.Qualified_Expression):
          self.__collect_names_from_iir(nodes.Get_Expression(iir), names, visited)
          return

      if kind == Iir_Kind.Aggregate:
          assoc = nodes.Get_Association_Choices_Chain(iir)
          while assoc != 0:
              self.__collect_names_from_iir(nodes.Get_Associated_Expr(assoc), names, visited)
              assoc = nodes.Get_Chain(assoc)
          return

      if kind == Iir_Kind.Indexed_Name:
          self.__collect_names_from_iir(nodes.Get_Prefix(iir), names, visited)
          idx = nodes.Get_Index_List(iir)
          if idx != 0:
              item = nodes.Get_Nth_Element(idx, 0)
              i = 0
              while item != 0:
                  self.__collect_names_from_iir(item, names, visited)
                  i += 1
                  item = nodes.Get_Nth_Element(idx, i)
          return

      if kind == Iir_Kind.Slice_Name:
          self.__collect_names_from_iir(nodes.Get_Prefix(iir), names, visited)
          return

  def __walk_iir_statements(self, stmt_chain, inputs: set, outputs: set):
      stmt = stmt_chain
      while stmt != 0:
          kind = nodes.Get_Kind(stmt)

          if kind == Iir_Kind.Simple_Signal_Assignment_Statement:
              target_names = set()
              self.__collect_names_from_iir(nodes.Get_Target(stmt), target_names)
              outputs.update(target_names)
              waveform = nodes.Get_Waveform_Chain(stmt)
              while waveform != 0:
                  self.__collect_names_from_iir(nodes.Get_We_Value(waveform), inputs)
                  waveform = nodes.Get_Chain(waveform)

          elif kind == Iir_Kind.Variable_Assignment_Statement:
              target_names = set()
              self.__collect_names_from_iir(nodes.Get_Target(stmt), target_names)
              outputs.update(target_names)
              self.__collect_names_from_iir(nodes.Get_Expression(stmt), inputs)

          elif kind == Iir_Kind.If_Statement:
              self.__collect_names_from_iir(nodes.Get_Condition(stmt), inputs)
              self.__walk_iir_statements(nodes.Get_Sequential_Statement_Chain(stmt), inputs, outputs)
              clause = nodes.Get_Else_Clause(stmt)
              while clause != 0:
                  cond = nodes.Get_Condition(clause)
                  if cond != 0:
                      self.__collect_names_from_iir(cond, inputs)
                  self.__walk_iir_statements(nodes.Get_Sequential_Statement_Chain(clause), inputs, outputs)
                  clause = nodes.Get_Else_Clause(clause)

          elif kind == Iir_Kind.Case_Statement:
              self.__collect_names_from_iir(nodes.Get_Expression(stmt), inputs)
              alt = nodes.Get_Case_Statement_Alternative_Chain(stmt)
              while alt != 0:
                  self.__walk_iir_statements(nodes.Get_Associated_Chain(alt), inputs, outputs)
                  alt = nodes.Get_Chain(alt)

          elif kind in (Iir_Kind.For_Loop_Statement, Iir_Kind.While_Loop_Statement):
              self.__walk_iir_statements(nodes.Get_Sequential_Statement_Chain(stmt), inputs, outputs)

          stmt = nodes.Get_Chain(stmt)

  def analyze_process(self, process) -> dict:
      iir = process._iirNode
      inputs  = set()
      outputs = set()
      for sig in process.SensitivityList:
        inputs.add(sig.NormalizedIdentifier)
      # Statements
      stmt_chain = nodes.Get_Sequential_Statement_Chain(iir)
      self.__walk_iir_statements(stmt_chain, inputs, outputs)
      inputs = inputs - outputs
      return {"inputs": inputs, "outputs": outputs}

This correctly returns the inputs and outputs as follow

[DEBUG]:  Process: None, sysitivity list = [Name: 'clk']
[DEBUG]:    Analyzed : {'inputs': {'g', 's', 'clk'}, 'outputs': {'d'}} 

I would love to have this features directly in the pyVHDLModel since i can develop my tool entirely against the pyVHDLModel and then move to a different backend in the future. I am availabe to put in some effort, with some time limitation, into it.

Is it something that you see useful to be added to the model ? I would love to have some gudiance on understanding a bit more how pyVHDLModel handles that since my approach has been to look at the classes code and "guess" the information that i need in a very iterative process.

[el3ctrician]

so i did some trails and i managed to get it in a pure pyVHDLModel without parsing the IIR as follows:

def __get_process_info(self,proc):
    inputs = set()
    outputs = set()
    infos = {"inputs" : inputs, "outputs": outputs}
    for sig_name in proc.SensitivityList:
        inputs.add(sig_name.Identifier)
    # Analyze all sequential statements for read signals
    for stmt in proc.Statements:
        self.__parse_process_statement(stmt, infos)
    infos["inputs"] = infos["inputs"] - infos["outputs"]
    return infos


  def __parse_process_statement(self,stmt,infos):
    # If parsing
    if isinstance(stmt,SequentialSimpleSignalAssignment):
      infos['outputs'].add(stmt.Target.Identifier)
      for waveform in stmt.Waveform:
        infos['inputs'].add(waveform.Expression.LeftOperand.Name.Identifier)
        infos['inputs'].add(waveform.Expression.RightOperand.Name.Identifier)

    elif isinstance(stmt, IfStatement):
        for sub_stmt in stmt.IfBranch.Statements:
          self.__parse_if_condition(stmt.IfBranch.Condition,infos)
          self.__parse_process_statement(sub_stmt,infos)
        for branch in stmt.ElsIfBranches:
          self.__parse_if_condition(branch.Condition,infos)
          for sub_stmt in branch.Statements:
            self.__parse_process_statement(sub_stmt,infos)
        if stmt.ElseBranch:
          for sub_stmt in stmt.ElseBranch.Statements:
              self.__parse_process_statement(sub_stmt,infos)
    else:
      warning(f"Found statement as {type(stmt)}")

  def __parse_if_condition(self,condition,infos):
    if isinstance(condition, SimpleName):
      infos['inputs'].add(condition.Identifier)
    elif hasattr(condition,"LeftOperand"):
      self.__parse_if_condition(condition.LeftOperand.Name, infos)
    elif hasattr(condition.Name,"Associations"):
      for ass in condition.Name.Associations:
        self.__parse_if_condition(ass.Name, infos)

that produces

[DEBUG]:   Process Infos {'inputs': {'clk', 'g', 's'}, 'outputs': {'d'}}

my issue now is since i am coming from VHDL world i don't really understand AST/Parset concept so i have to analyze each class type and understand it. Is there's something like a map between VHDL statments and the model ? i think the autogenerated python documation is ok but it's dosen't say which part of VHDL is mapped to what so it's a bit too much for me.

Thanks

[Paebbels]

Hi,

read signals of a process (I would call them maybe used signals) are:

• signals in sensitivity list
• signals on the right-hand-side (RHS) in an assignment.

While synthesizers might ignore the sensitivity list, simulators don't. You can have a mismatch between sensitivity list and read signals. Either nor all are listed (mismatch between synthesis and simulation model) or they list more. On one hand this can be a slow down (too many process wakeups) or by intention.

Every signal in the sensitivity list translates to a signal in a wait on <sensitivity list>; statement in the process as a last statement.

process(Reset, Clock)
begin
  -- ...
end process;

transforms to:

process
begin
  -- ...
  wait on Reset, Clock;
end process;

Therefore I would call the full set of needed inputs to a process UsedSignals. I'm not sure if the LRM distinguishes used from read signals. The counter part would be Drivers, for all written signals.

---

The process is declared as follows:

class ProcessStatement(
  ConcurrentStatement,
  SequentialDeclarationsMixin,
  SequentialStatementsMixin,
  DocumentedEntityMixin
):

Thus, it has a sequential declaration region (local objects like constants, variables and files) as well a sequential statements. In the latter you'll find e.g. your assignments. Of cause, assignments can be nested in other statements like if-statements, case-statements, loops, etc.

So would would traverse all statements and if it's a compound statements (one that has nested statements) you would descend in a DFS (depth first search) order.

Such a functionality would be provided by pyVHDLModel, but not the frontend like pyGHDL.dom. The latter would parse GHDL's IIR and create the tree of statements in a process. pyGHDL.dom can already tarnslate expressions and if I recall correctly, it can also translate some assignments. Unfortunately, VHDL has many different assignment variants. concurrent assignments, sequential assignments, selected assignment, signal assignment, variable assignment, ... and combinations thereof.

---

__get_iir_name already exists in pyGHDL.dom as GetNameOfNode.

I don't recall all implemented / non-yet-implemented parts of pyGHDL.dom, bu I see many implemented features in Squential.py like SequentialSimpleSignalAssignment or WaitStatement. Have you tried accessing what's already provided by pyGHDL.dom for a ProcessStatement?

[el3ctrician]

Hi,
thanks for all the information. I asked Claude to come up with a table with how things are mapped between VHDL world and PyVHDLModel based on _Translate.py from GHDL and it came up with this:

pyGHDL DOM — VHDL → Class Mapping Reference

Source: pyGHDL/dom/_Translate.py
All classes live under pyGHDL.dom.* and implement pyVHDLModel interfaces.

---

Sequential Statements

Dispatcher: GetSequentialStatementsFromChainedNodes() → pyGHDL.dom.Sequential

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
if ... then ... elsif ... else ... end if;	If_Statement	IfStatement	.IfBranch.Condition, .IfBranch.Statements, .ElsIfBranches[], .ElseBranch
case x is when ... end case;	Case_Statement	CaseStatement	.SelectExpression, .Cases[]
for i in r loop ... end loop;	For_Loop_Statement	ForLoopStatement	.LoopIndex, .Range, .Statements
while cond loop ... end loop;	While_Loop_Statement	WhileLoopStatement	.Condition, .Statements
sig <= expr;	Simple_Signal_Assignment_Statement	SequentialSimpleSignalAssignment	.Target, .Waveform[]
var := expr;	Variable_Assignment_Statement	⚠️ NotImplemented (warning only)	—
sig <= expr when cond else ...;	Conditional_Signal_Assignment_Statement	⚠️ NotImplemented	—
var := expr when cond else ...;	Conditional_Variable_Assignment_Statement	⚠️ NotImplemented	—
wait [on ...] [until ...] [for ...];	Wait_Statement	WaitStatement	.SensitivityList, .Condition, .Timeout
proc_call(...);	Procedure_Call_Statement	SequentialProcedureCall	.Procedure, .ParameterMappings
report "..." severity ...;	Report_Statement	SequentialReportStatement	.Message, .Severity
assert cond report "...";	Assertion_Statement	SequentialAssertStatement	.Condition, .Message, .Severity
null;	Null_Statement	NullStatement	—
next [label] [when cond];	Next_Statement	NextStatement	.LoopLabel, .Condition
exit [label] [when cond];	Exit_Statement	ExitStatement	.LoopLabel, .Condition

---

Concurrent Statements

Dispatcher: GetConcurrentStatementsFromChainedNodes() → pyGHDL.dom.Concurrent

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
process (clk, ...) ... end process;	Sensitized_Process_Statement	ProcessStatement	.SensitivityList, .Statements, .DeclaredItems
process ... end process; (no sensitivity)	Process_Statement	ProcessStatement	.SensitivityList = None, .Statements, .DeclaredItems
sig <= expr; (concurrent)	Concurrent_Simple_Signal_Assignment	ConcurrentSimpleSignalAssignment	.Target, .Waveform
sig <= expr when cond else ...;	Concurrent_Conditional_Signal_Assignment	⚠️ NotImplemented	—
with sel select sig <= ...;	Concurrent_Selected_Signal_Assignment	⚠️ NotImplemented	—
proc_call(...); (concurrent)	Concurrent_Procedure_Call_Statement	ConcurrentProcedureCall	.Procedure, .ParameterMappings
label: entity lib.Ent(arch) port map(...)	Component_Instantiation_Statement + Entity_Aspect_Entity	EntityInstantiation	.Entity, .GenericMappings, .PortMappings
label: configuration lib.Cfg port map(...)	Component_Instantiation_Statement + Entity_Aspect_Configuration	ConfigurationInstantiation	.Configuration, .GenericMappings, .PortMappings
label: CompName port map(...)	Component_Instantiation_Statement + Simple_Name / Selected_Name	ComponentInstantiation	.Component, .GenericMappings, .PortMappings
label: block ... end block;	Block_Statement	ConcurrentBlockStatement	.DeclaredItems, .Statements
if cond generate ... end generate;	If_Generate_Statement	IfGenerateStatement	.IfBranch, .ElsIfBranches, .ElseBranch
case expr generate when ... end generate;	Case_Generate_Statement	CaseGenerateStatement	.SelectExpression, .Cases
for i in range generate ... end generate;	For_Generate_Statement	ForGenerateStatement	.LoopIndex, .Range, .Statements
assert cond; (PSL concurrent)	Psl_Assert_Directive	ConcurrentAssertStatement	.Condition, .Message
x == y; (AMS simultaneous)	Simple_Simultaneous_Statement	⚠️ NotImplemented	—

---

Expressions

Dispatcher: GetExpressionFromNode() via __EXPRESSION_TRANSLATION dict
Classes live in pyGHDL.dom.Expression unless marked [Symbol] (pyGHDL.dom.Symbol) or [Literal] (pyGHDL.dom.Literal)

Names & Symbols

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
sig_name (bare signal/variable name)	Simple_Name	SimpleObjectOrFunctionCallSymbol [Symbol]	.Name.Identifier
pkg.name / arr(i) / attr'name / f(x)	Selected_Name, Attribute_Name, Parenthesis_Name	IndexedObjectOrFunctionCallSymbol [Symbol]	.Name → SelectedName / ParenthesisName / AttributeName

Note on function calls: rising_edge(clk) has Iir_Kind.Parenthesis_Name and becomes
IndexedObjectOrFunctionCallSymbol. Access arguments via .Name.Associations[].

Literals

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
null	Null_Literal	NullLiteral [Literal]	—
42	Integer_Literal	IntegerLiteral [Literal]	.Value
3.14	Floating_Point_Literal	FloatingPointLiteral [Literal]	.Value
10 ns	Physical_Int_Literal	PhysicalIntegerLiteral [Literal]	.Value, .Unit
1.5 ns	Physical_Fp_Literal	PhysicalFloatingLiteral [Literal]	.Value, .Unit
'A'	Character_Literal	CharacterLiteral [Literal]	.Value
"hello"	String_Literal8	StringLiteral [Literal]	.Value

Unary Operators

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
+a	Identity_Operator	IdentityExpression	.Operand
-a	Negation_Operator	NegationExpression	.Operand
abs a	Absolute_Operator	AbsoluteExpression	.Operand
not a	Not_Operator	InverseExpression	.Operand
(expr)	Parenthesis_Expression	ParenthesisExpression	.Operand

Logical Operators

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
a and b	And_Operator	AndExpression	.LeftOperand, .RightOperand
a nand b	Nand_Operator	NandExpression	.LeftOperand, .RightOperand
a or b	Or_Operator	OrExpression	.LeftOperand, .RightOperand
a nor b	Nor_Operator	NorExpression	.LeftOperand, .RightOperand
a xor b	Xor_Operator	XorExpression	.LeftOperand, .RightOperand
a xnor b	Xnor_Operator	XnorExpression	.LeftOperand, .RightOperand

Relational Operators

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
a = b	Equality_Operator	EqualExpression	.LeftOperand, .RightOperand
a /= b	Inequality_Operator	UnequalExpression	.LeftOperand, .RightOperand
a < b	Less_Than_Operator	LessThanExpression	.LeftOperand, .RightOperand
a <= b	Less_Than_Or_Equal_Operator	LessEqualExpression	.LeftOperand, .RightOperand
a > b	Greater_Than_Operator	GreaterThanExpression	.LeftOperand, .RightOperand
a >= b	Greater_Than_Or_Equal_Operator	GreaterEqualExpression	.LeftOperand, .RightOperand
a ?= b	Match_Equality_Operator	MatchingEqualExpression	.LeftOperand, .RightOperand
a ?/= b	Match_Inequality_Operator	MatchingUnequalExpression	.LeftOperand, .RightOperand
a ?< b	Match_Less_Than_Operator	MatchingLessThanExpression	.LeftOperand, .RightOperand
a ?<= b	Match_Less_Than_Or_Equal_Operator	MatchingLessEqualExpression	.LeftOperand, .RightOperand
a ?> b	Match_Greater_Than_Operator	MatchingGreaterThanExpression	.LeftOperand, .RightOperand
a ?>= b	Match_Greater_Than_Or_Equal_Operator	MatchingGreaterEqualExpression	.LeftOperand, .RightOperand

Arithmetic Operators

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
a + b	Addition_Operator	AdditionExpression	.LeftOperand, .RightOperand
a - b	Substraction_Operator	SubtractionExpression	.LeftOperand, .RightOperand
a * b	Multiplication_Operator	MultiplyExpression	.LeftOperand, .RightOperand
a / b	Division_Operator	DivisionExpression	.LeftOperand, .RightOperand
a mod b	Modulus_Operator	ModuloExpression	.LeftOperand, .RightOperand
a rem b	Remainder_Operator	RemainderExpression	.LeftOperand, .RightOperand
a ** b	Exponentiation_Operator	ExponentiationExpression	.LeftOperand, .RightOperand
a & b	Concatenation_Operator	ConcatenationExpression	.LeftOperand, .RightOperand

Shift / Rotate Operators

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
a sll b	Sll_Operator	ShiftLeftLogicExpression	.LeftOperand, .RightOperand
a srl b	Srl_Operator	ShiftRightLogicExpression	.LeftOperand, .RightOperand
a sla b	Sla_Operator	ShiftLeftArithmeticExpression	.LeftOperand, .RightOperand
a sra b	Sra_Operator	ShiftRightArithmeticExpression	.LeftOperand, .RightOperand
a rol b	Rol_Operator	RotateLeftExpression	.LeftOperand, .RightOperand
a ror b	Ror_Operator	RotateRightExpression	.LeftOperand, .RightOperand

Other Expressions

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
l to/downto r	Range_Expression	RangeExpression	.LeftBound, .RightBound, .Direction
t'(expr)	Qualified_Expression	QualifiedExpression	.TypeMark, .Operand
(a => x, others => y)	Aggregate	Aggregate	.Elements[]
new subtype	Allocator_By_Subtype	SubtypeAllocation	.Subtype
new type'(expr)	Allocator_By_Expression	QualifiedExpressionAllocation	.Expression

---

Names (pyGHDL.dom.Name)

Used inside expressions and as targets/prefixes. Produced by GetName().

VHDL Construct	Iir_Kind	pyGHDL DOM Class	Key Attributes
sig	Simple_Name	SimpleName	.Identifier
pkg.item	Selected_Name	SelectedName	.Identifier, .Prefix
name(assoc, ...)	Parenthesis_Name	ParenthesisName	.Prefix, .Associations[]
name'attr	Attribute_Name	AttributeName	.Identifier, .Prefix
name.all	Selected_By_All_Name	AllName	.Prefix
open (in associations)	—	OpenName	—

---

Quick Reference: Extracting Signal Names from Expressions

from pyGHDL.dom.Symbol import SimpleObjectOrFunctionCallSymbol, IndexedObjectOrFunctionCallSymbol
from pyGHDL.dom.Expression import (OrExpression, AndExpression, ...)  # any binary
from pyGHDL.dom.Name import ParenthesisName
 
def collect_names(expr, names: set):
    if expr is None:
        return
    # bare name: g, s, clk  →  SimpleObjectOrFunctionCallSymbol
    if isinstance(expr, SimpleObjectOrFunctionCallSymbol):
        names.add(expr.Name.Identifier)
    # function call / indexed: rising_edge(clk), arr(i)
    elif isinstance(expr, IndexedObjectOrFunctionCallSymbol):
        if isinstance(expr.Name, ParenthesisName):
            for assoc in (expr.Name.Associations or []):
                collect_names(assoc, names)
    # binary expressions: LeftOperand op RightOperand
    elif hasattr(expr, "LeftOperand") and hasattr(expr, "RightOperand"):
        collect_names(expr.LeftOperand, names)
        collect_names(expr.RightOperand, names)
    # unary expressions
    elif hasattr(expr, "Operand"):
        collect_names(expr.Operand, names)
    # literals → no signal names, ignore

---

⚠️ Not Implemented in pyGHDL DOM

These constructs emit a WarningCollector warning and are skipped (not raised as errors):

VHDL Construct	Iir_Kind
Sequential variable assignment	Variable_Assignment_Statement
Sequential conditional signal assignment	Conditional_Signal_Assignment_Statement
Sequential conditional variable assignment	Conditional_Variable_Assignment_Statement
Concurrent conditional signal assignment	Concurrent_Conditional_Signal_Assignment
Concurrent selected signal assignment	Concurrent_Selected_Signal_Assignment
AMS simultaneous statement	Simple_Simultaneous_Statement
Configuration specification	Configuration_Specification
Group declaration / template	Group_Declaration, Group_Template_Declaration
Disconnect specification	Disconnection_Specification
AMS nature / quantity / terminal	Nature_Declaration, *_Quantity_Declaration, Terminal_Declaration

using this i was able to fetch the process meta information needed as :

  def __get_process_info(self, proc):
      inputs  = set()
      outputs = set()
      infos   = {"inputs": inputs, "outputs": outputs}

      for sig_name in (proc.SensitivityList or []):
          inputs.add(sig_name.Identifier)

      for stmt in (proc.Statements or []):
          self.__parse_process_statement(stmt, infos)

      infos["inputs"] = infos["inputs"] - infos["outputs"]
      return infos

  def __parse_process_statement(self, stmt, infos):
      if isinstance(stmt, SequentialSimpleSignalAssignment):
          # Target is always a SimpleObjectOrFunctionCallSymbol for plain signals
          infos['outputs'].add(stmt.Target.Identifier)
          for waveform in (stmt.Waveform or []):
              self.__collect_names_from_expr(waveform.Expression, infos['inputs'])

      elif isinstance(stmt, IfStatement):
          self.__collect_names_from_expr(stmt.IfBranch.Condition, infos['inputs'])
          for sub in (stmt.IfBranch.Statements or []):
              self.__parse_process_statement(sub, infos)
          for branch in (stmt.ElsIfBranches or []):
              self.__collect_names_from_expr(branch.Condition, infos['inputs'])
              for sub in (branch.Statements or []):
                  self.__parse_process_statement(sub, infos)
          if stmt.ElseBranch:
              for sub in (stmt.ElseBranch.Statements or []):
                  self.__parse_process_statement(sub, infos)

      elif isinstance(stmt, CaseStatement):
          self.__collect_names_from_expr(stmt.SelectExpression, infos['inputs'])
          for case in (stmt.Cases or []):
              for sub in (getattr(case, 'Statements', None) or []):
                  self.__parse_process_statement(sub, infos)

      elif isinstance(stmt, (ForLoopStatement, WhileLoopStatement)):
          for sub in (stmt.Statements or []):
              self.__parse_process_statement(sub, infos)

      elif isinstance(stmt, SequentialProcedureCall):
          # procedure calls can read signals as arguments
          for assoc in (stmt.ParameterMappings or []):
              self.__collect_names_from_expr(getattr(assoc, 'ActualPart', None), infos['inputs'])

      elif isinstance(stmt, (NullStatement, NextStatement, ExitStatement,
                            SequentialAssertStatement, SequentialReportStatement,WaitStatement)):
          debug(f"Ignoring non Synthesizable statement {stmt}")



  def __collect_names_from_expr(self, expr, names: set):
      """
      Recursively collect all signal/variable names READ in an expression.
      Based directly on pyGHDL.dom._Translate.__EXPRESSION_TRANSLATION.
      """
      if expr is None:
          return

      # Iir_Kind.Simple_Name → SimpleObjectOrFunctionCallSymbol
      if isinstance(expr, SimpleObjectOrFunctionCallSymbol):
          # .Name is a SimpleName whose .Identifier is the string
          names.add(expr.Name.Identifier)
          return

      # --- Function call or indexed name: `rising_edge(clk)`, `arr(i)` ---
      # Iir_Kind.Parenthesis_Name / Selected_Name / Attribute_Name
      # → IndexedObjectOrFunctionCallSymbol
      if isinstance(expr, IndexedObjectOrFunctionCallSymbol):
          # Recurse into the prefix (the function/array name itself is not a signal read)
          # and into each association (the actual arguments ARE reads)
          name = expr.Name
          if isinstance(name, ParenthesisName):
              for assoc in (name.Associations or []):
                  self.__collect_names_from_expr(assoc, names)
          elif isinstance(name, (SimpleName, SelectedName, AttributeName)):
              # selected name like pkg.func — prefix might be a signal
              pass
          return

      # --- Binary expressions: LeftOperand op RightOperand ---
      _BINARY = (
          AndExpression, NandExpression, OrExpression, NorExpression,
          XorExpression, XnorExpression,
          AdditionExpression, SubtractionExpression,
          MultiplyExpression, DivisionExpression,
          ModuloExpression, RemainderExpression,
          ExponentiationExpression, ConcatenationExpression,
          EqualExpression, UnequalExpression,
          LessThanExpression, LessEqualExpression,
          GreaterThanExpression, GreaterEqualExpression,
          ShiftLeftLogicExpression, ShiftRightLogicExpression,
          ShiftLeftArithmeticExpression, ShiftRightArithmeticExpression,
          RotateLeftExpression, RotateRightExpression,
      )
      if isinstance(expr, _BINARY):
          self.__collect_names_from_expr(expr.LeftOperand, names)
          self.__collect_names_from_expr(expr.RightOperand, names)
          return

      # --- Unary expressions ---
      if isinstance(expr, (NegationExpression, InverseExpression,
                          IdentityExpression, AbsoluteExpression)):
          self.__collect_names_from_expr(expr.Operand, names)
          return

      # --- Parenthesis: (expr) ---
      if isinstance(expr, ParenthesisExpression):
          self.__collect_names_from_expr(expr.Operand, names)
          return

      # --- Qualified expression: type'(expr) ---
      if isinstance(expr, QualifiedExpression):
          self.__collect_names_from_expr(expr.Operand, names)
          return

      # --- Range: left to/downto right ---
      if isinstance(expr, RangeExpression):
          self.__collect_names_from_expr(expr.LeftBound, names)
          self.__collect_names_from_expr(expr.RightBound, names)
          return

      # --- Aggregate: (a => x, b => y, others => z) ---
      if isinstance(expr, Aggregate):
          for elem in (expr.Elements or []):
              self.__collect_names_from_expr(getattr(elem, "Expression", None), names)
          return

and it seems to be working for me.

Let me know if we want to add this to the pyVHDLModel as meta information for each process statment. I am more than happy to structure my code for a pull request

[Paebbels]

How, this must have used lot's of tokens to read and process all the code :) I admit it's a nice summary.

One remark on:

      # --- Binary expressions: LeftOperand op RightOperand ---
      _BINARY = (
          AndExpression, NandExpression, OrExpression, NorExpression,
          ...
          RotateLeftExpression, RotateRightExpression,
      )
      if isinstance(expr, _BINARY):

Operators form a inheritance hierarchy and you can just test on BinaryExpression in isinstance. Same for UnaryExpression.

---

Mistakes by Claude:

• Handling of SimpleObjectOrFunctionCallSymbol and IndexedObjectOrFunctionCallSymbol is not correct. First the symbol must be resolved to know if it's an object (signal, variable, constant, file) or a function call.
  • _LinkSymbolsInExpression should resolve these symbols, but I don't recall if this was already tested.
    • SimpleObjectOrFunctionCallSymbol needs an overwritten getter/setter for Reverence, to set the function reference. This is needed to change the possible references list to Function only.
      Maybe a read-only IsFunction property should be added, too.
    • Similar for IndexedObjectOrFunctionCallSymbol.
• RangeExpression cannot contribute to read signals, because it would be in a slice, which need to be static.

---

You could start at ProcessStatement:

• A read-only property for UsedSignals: a set of sensitivity list signals and read signals
• A read-only property for ReadSignals: a set of read signals
• A read-only property for AssignedSignals: a set of signals used as targets in assignments.
• An IndexSignals method to traverse local statements.

Questions:

• What about signals (or other objects used to to derive locally declared objects like vector sizes?

[el3ctrician]

How, this must have used lot's of tokens to read and process all the code :) I admit it's a nice summary.

I used the free version startigically giving it all the infos needed from the code. I was just too short on time to write it myself :)

One remark on:

  # --- Binary expressions: LeftOperand op RightOperand ---
  _BINARY = (
      AndExpression, NandExpression, OrExpression, NorExpression,
      ...
      RotateLeftExpression, RotateRightExpression,
  )
  if isinstance(expr, _BINARY):

Operators form a inheritance hierarchy and you can just test on BinaryExpression in isinstance. Same for UnaryExpression.

i remember doing this and for some reason didn't work but i will try again later

Mistakes by Claude:

• Handling of SimpleObjectOrFunctionCallSymbol and IndexedObjectOrFunctionCallSymbol is not correct. First the symbol must be resolved to know if it's an object (signal, variable, constant, file) or a function call.

  • _LinkSymbolsInExpression should resolve these symbols, but I don't recall if this was already tested.

* `SimpleObjectOrFunctionCallSymbol` needs an overwritten getter/setter for `Reverence`, to set the function reference. This is needed to change the possible references list to `Function` only.
  Maybe a read-only `IsFunction` property should be added, too.
* Similar for `IndexedObjectOrFunctionCallSymbol`.

• RangeExpression cannot contribute to read signals, because it would be in a slice, which need to be static.

I also noticed other issues but just wanted to share my progress so far to make sure i am moving in the right direction. For sure it will need better understanding.

You could start at ProcessStatement:

• A read-only property for UsedSignals: a set of sensitivity list signals and read signals
• A read-only property for ReadSignals: a set of read signals
• A read-only property for AssignedSignals: a set of signals used as targets in assignments.
• An IndexSignals method to traverse local statements.

great ! i like the names !

Questions:

• What about signals (or other objects used to to derive locally declared objects like vector sizes?

i would say that a Signal is a Signal being local or global it must have the scope of the architecture and hence could potenitally be accessed one day from another process/inst. etc. Since the goal is to provide a list of "inputs" and "outputs" of a process (in my head a process is a piece of digital circuit with inputs and outputs musch like an instance of a component) so regardless of its usage it still falls under this category for me. Different story are local variables which i still didn't play with yet in my tests

[Paebbels]

I wouldn't consider signal usages like this as an input

process
  constant BITS : positive := AddressBus'length;
begin

end process.

Here we're not accessing the AddressBus' changing value, but a constant associated with that signal line known by the compiler. We're accessing compile time information. Maybe we can find another category to also have these signals included, because it will be part of the dependency graph, but I wouldn't consider these usages an input or read signal.

[el3ctrician]

is this the only instance where you access the AddressBus in the whole process ? if yes then i agree but i think that i will not be parsing constants definition or any local variables. Thant being said i agree on the fact that if you only, through out the whole process, don't access the signal but only it's attributes then it shall not be used in the list. Maybe we have something for attributes that we can exclude ? maybe exclude the class AttributeName ?

[Paebbels]

is this the only instance where you access the AddressBus in the whole process?

My point was: not every signal is used for reading it's value. Of cause if there are multiple uses (that's why you proposed a set()) might overlap and then a "real" usage appears in the process' code. This corner case isn't limited to constant declarations, it could also be used in an expression:

process
begin
  counter <= counter + AddressBus'length;
end process;

I think your point of looking at the AttributeName is more precise. Because the signal is just a path element on the way to get a constant value denoted by the attribute.

But ...
Some attributes can be signals: see 'delayed :)

[el3ctrician]

good point about 'delayed i was focused on the synthesizable code for now ... i think then we can parse the AttributeName for a decision on which qualifies as signal and what does not

[Paebbels]

@el3ctrician pyVHDLModel got a huge update finishing almost every open item it had. Currently, pyGHDL.dom has a big PR pending at GHDL (ghdl/ghdl#3313).