iommu: qcom: Add iommu-debug framework - #2
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Add AEST RAS error source nodes for the Monaco SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/all/20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Add pinctrl states for the GP M/N divider clock output pin across multiple Qualcomm SoCs: wire it to the GP M/N clock controller node via pinctrl-0. - kodiak (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). - lemans (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). - monaco (qcs8300): Add gp_mn_active state on gpio32 (gp_mn function). Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…75P and QCS8300 Add the GP M/N divider clock controller node at 0x088d3000 to the SA8775P (kodiak, lemans) and QCS8300 (monaco) SoC device trees. The node uses the qcom,clk-gp-mnd compatible, is clocked by the PDM XO4 and AHB clocks from GCC, and exposes a single clock output (gp_mn_clk) on the dedicated gp_mn pin mux function. The XO4 clock is pre-assigned to 4.8 MHz (XO/4). Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…no SMMU On Monaco platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-5-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
… devices Add label properties to TPDM and CTI nodes in the monaco device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/linux-arm-msm/20260414-add-label-to-coresight-device-v2-3-5017d07358f2@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
… nodes The MCP251XFD can expose two pins as GPIOs. The binding already declares gpio-controller and #gpio-cells for the device. Whitelist GPIO hog child nodes using patternProperties so boards can set default GPIO states at boot via DT, consistent with other GPIO controllers (e.g. microchip,mpfs-gpio). Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260108125200.2803112-2-viken.dadhaniya@oss.qualcomm.com/
Enable Qualcomm BCL hardware devicetree binding configuration for pm8350c. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-4-7b426f0b77a1@oss.qualcomm.com
Enable Qualcomm BCL hardware devicetree binding configuration for pm7250b. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-3-7b426f0b77a1@oss.qualcomm.com
…t Alt Mode Add the mode-switch property to the QMP combo PHY so that mode-switch events are routed to it, allowing the PHY to enter DisplayPort Alternate Mode. Expand the DP data-lanes assignment from two to four lanes to make use of the full link bandwidth available in this configuration. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260420-kodiak_4k-v1-1-83dfc66b8f06@oss.qualcomm.com/
…te heap On KODIAK platforms boot can fail when the DT "adsp-rpc-remote-heap" reserved-memory region overlaps with firmware allocations (UEFI/EFI runtime). The kernel then reports failure to reserve the region and subsequent EFI runtime activity may trigger aborts. The remote heap node was described as a fixed "no-map" region, which turns it into a hard carveout. Replace it with a "shared-dma-pool" reserved memory region with reusable CMA-backed allocation, specifying alignment and size. This avoids hard carveouts and reduces the chance of conflicting with firmware memory maps while keeping an explicit pool for ADSP remote heap usage. Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com>
Enable secondary mi2s to support HDMI audio. Link: https://lore.kernel.org/all/20260413091937.134469-2-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
Add new dai link to enable DP audio. Link: https://lore.kernel.org/all/20260413091937.134469-3-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
… and record for qcs6490-rb3gen2 industrial mezzanine Add WCD playback and capture DAI link to sound node. Add WCD codec node and corresponding soundwire nodes to perform headset playback and record. Link: https://lore.kernel.org/all/20260423071951.3181130-1-karthik.s@oss.qualcomm.com/#t Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
…on slots Some workloads on Kodiak can exhaust FastRPC sessions when multiple compute clients open contexts concurrently, leading to -EBUSY failures. Describe the compute context bank with qcom,nsessions = <5> so the driver can provision enough session slots for the compute-cb instance. Link: https://lore.kernel.org/all/20260401073345.478-1-jianping.li@oss.qualcomm.com/ Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com>
…no SMMU On Kodiak platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-3-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
… devices Add label properties to TPDM and CTI nodes in the kodiak device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/linux-arm-msm/20260414-add-label-to-coresight-device-v2-4-5017d07358f2@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
All the existing variants Kodiak boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Kodiak IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. Note that modem and media subsystems haven't been supported yet due to missing dependencies. For GPU to work, zap shader is disabled and in EL2 mode the kernel owns hardware watchdog which is enabled here. And for wifi to work wpss copy engine memory need to be mapped for WPSS firmware to work which is aligning with sc7280 chrome. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Link: https://lore.kernel.org/all/20260624063952.2242702-1-mukesh.ojha@oss.qualcomm.com/ Co-developed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Enable IPA and ensure ipa apps loads the gsi firmware because modem doesn't support IPA FW loading. Link: https://lore.kernel.org/all/20260618124700.2001191-1-sarat.addepalli@oss.qualcomm.com/ Signed-off-by: Sarat Addepalli <sarat.addepalli@oss.qualcomm.com> Signed-off-by: Pavan Kumar M <rpavan@qti.qualcomm.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260514-arm-psci-system_reset2-vendor-reboots-v22-6-28a5bde07483@oss.qualcomm.com
Currently valid mode checks are only for hdisplay and vdisplay, add htotal and vtotal to filter only specific modes. Link:https://lore.kernel.org/lkml/20251126-lt9611uxc-modes-v2-1-34bf9b351921@oss.qualcomm.com/ Signed-off-by: Nilesh Laad <nilesh.laad@oss.qualcomm.com> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Add 3840x2160@30 mode in lt9611uxc modes to add support for 4K@30 resolution. Link:https://lore.kernel.org/r/20251126-lt9611uxc-4k30-v2-1-3de0ea58c24e@oss.qualcomm.com Signed-off-by: Nilesh Laad <nilesh.laad@oss.qualcomm.com> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
…o HDMI driver LT9611C(EX/UXD) is an I2C-controlled chip that Receiver signal/dual port mipi dsi and output hdmi, differences in hardware features: - LT9611C: supports 1-port mipi dsi to hdmi 1.4 - LT9611EX: supports 2-port mipi dsi to hdmi 1.4 - LT9611UXD: supports 2-port mipi dsi to hdmi 1.4/2.0 Link : https://lore.kernel.org/lkml/20260508134009.4582-3-syyang@lontium.com/ Signed-off-by: Sunyun Yang <syyang@lontium.com> Signed-off-by: Mohit Dsor <mohit.dsor@oss.qualcomm.com>
…iver LT9611C(EX/UXD) is an I2C-controlled chip that Receiver signal/dual port mipi dsi and output hdmi, differences in hardware features: - LT9611C: supports 1-port mipi dsi to hdmi 1.4 - LT9611EX: supports 2-port mipi dsi to hdmi 1.4 - LT9611UXD: supports 2-port mipi dsi to hdmi 1.4/2.0 Link : https://lore.kernel.org/lkml/20260508134009.4582-3-syyang@lontium.com/ Signed-off-by: Sunyun Yang <syyang@lontium.com> Signed-off-by: Mohit Dsor <mohit.dsor@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
The cached drm_edid seems unnecessary here. Use the drm_edid pointer directly in the plug stage instead of caching it. Remove the cached drm_edid and the corresponding oneliner to simplify the code. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-1-ea04113e8233@oss.qualcomm.com/
The bridge .mode_set() callback is deprecated. Remove it and move all mode setup logic to .atomic_enable(), where the adjusted_mode is available from the atomic CRTC state. Drop msm_dp_mode from msm_dp_display_private and store the mode directly in the panel, as it was only used as a temporary cache. Both changes are limited to msm_dp_display_set_mode and are kept in a single patch. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-2-ea04113e8233@oss.qualcomm.com/
…fo() The display layer directly assigns msm_dp_panel mode fields (bpp, sync polarity, yuv420 flag) instead of letting the panel manage its own state. Pass adjusted_mode and bpp as parameters to msm_dp_panel_init_panel_info() and move the assignments inside it. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-3-ea04113e8233@oss.qualcomm.com/
… and stream parts The DP_CONFIGURATION_CTRL register contains both link-level and stream-specific fields. Currently, msm_dp_ctrl_config_ctrl() configures all of them together. Separate the configuration into link parts and stream parts to support MST. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-4-ea04113e8233@oss.qualcomm.com/
…te function Refactor the MISC1_MISC0 register configuration into a standalone helper function to support MST. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-5-ea04113e8233@oss.qualcomm.com/
msm_dp_ctrl_configure_source_params() should only handle stream-related configuration. Move the link setup out of it so MST can program link and stream settings separately. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-6-ea04113e8233@oss.qualcomm.com/
Enable/Disable of DP pixel clock happens in multiple code paths leading to code duplication. Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-7-ea04113e8233@oss.qualcomm.com/
On Nord's HS-only USB20 tile the QSCRATCH register interface is clocked by the eUSB2 PHY's UTMI clock. Writing the select-utmi-as-pipe-clk configuration from probe() happens before the PHY is initialized and faults with a synchronous external abort. Add per-compatible data to the driver. Initially it contains the defer_utmi_clk_sel flag - set it for qcom,nord-dwc3 - which tells the driver to request an early PHY init from DWC3 core. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The sa8255p vops (fw-managed variant) was missing the MCQ hooks, causing the driver to silently fall back to SDB mode even when MCQ resource is available. Wire up the same MCQ ops used by the standard qcom vops, so that MCQ mode works on sa8255p. Link: https://lore.kernel.org/r/20260728051104.675088-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit bae3eb11a976168bfc86637eeb8c16a940eaadcc)
Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc on Nord SoC. This includes: - SMEM memory reservation used by the inter-processor communication infrastructure - IPCC mailbox controller for inter-processor signalling - AOSS QMP node for load state power management - SMP2P nodes providing stop control and fault/crash interrupt signals - Remoteproc nodes with a GLINK edge and FastRPC compute contexts for userspace offload The embedded variant specific power domains, XO clock, and interconnect paths are filled in nord-embedded.dtsi. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit 74c9d774974e8f501c144e7dd7616980c5142b76)
Enable USB_0 on the RRD board with PTN3222 eUSB2 redriver on I2C9. Although FUSB15201 Type-C controller driver is missing, enabling usb-role-switch and "otg" mode still make it easier to test both host and device mode, by manually switching the mode via: /sys/kernel/debug/usb/a600000.usb/mode Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit 7a0811760458d895c8df827ad7a48e8fce4b6606)
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord RRD board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit fc4157d7a54d7dd74ee2f52b242c91604c464f4f)
With meta_8_3 build, usb_1/2 causes SMMU error like below. Disable them for now. [ 1.357502] Internal error: synchronous external abort: 0000000096000010 [#1] SMP ... [ 1.357536] Call trace: [ 1.357537] arm_smmu_write_sme+0x74/0x98 (P) [ 1.357539] arm_smmu_probe_device+0x25c/0x400 [ 1.357540] __iommu_probe_device+0xf4/0x4bc [ 1.357542] probe_iommu_group+0x3c/0x68 [ 1.357544] bus_for_each_dev+0x7c/0xdc [ 1.357546] iommu_device_register+0xd8/0x244 [ 1.357548] arm_smmu_device_probe+0xc98/0xf14 [ 1.357549] platform_probe+0x5c/0x9c [ 1.357550] really_probe+0xbc/0x29c [ 1.357552] __driver_probe_device+0x16c/0x19c [ 1.357555] driver_probe_device+0x3c/0x114 [ 1.357557] __driver_attach+0x90/0x180 [ 1.357559] bus_for_each_dev+0x7c/0xdc [ 1.357561] driver_attach+0x24/0x30 [ 1.357563] bus_add_driver+0xe4/0x208 [ 1.357565] driver_register+0x5c/0x124 [ 1.357566] __platform_driver_register+0x28/0x34 [ 1.357567] arm_smmu_init+0x30/0x74 [ 1.357572] do_one_initcall+0x80/0x1c8 [ 1.357574] kernel_init_freeable+0x208/0x2f0 [ 1.357576] kernel_init+0x2c/0x1e0 [ 1.357580] ret_from_fork+0x10/0x20 [ 1.357582] Code: f9400404 b5000104 f9400680 8b22c002 (b9000043) [ 1.357583] ---[ end trace 0000000000000000 ]--- Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> (cherry picked from commit 6a03ea8827c7a485ade5491548543284447204cd; retargeted nord-ride-embedded.dts -> nord-ride-sx.dts)
Enable OTG mode for USB_0 so that ADB over USB can work. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> (cherry picked from commit 70b11d132130f7da0537a372fc4641600bb3067d; retargeted nord-ride-embedded.dts -> nord-ride-sx.dts)
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord Ride Embedded board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> (cherry picked from commit 69550fda5029943df41d71ae6365a63d5a79e075; retargeted nord-ride-embedded.dts -> nord-ride-sx.dts)
added correct addrs for watchdog node Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Haritha S K <haritha.k@oss.qualcomm.com>
nord: Enable cpufreq cooling devices
…r on Nord SoC" This reverts commit a5604d4. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…ock Controller for Nord" This reverts commit 1141853. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
… driver for Nord" This reverts commit f7978ea. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…roller for Nord" This reverts commit 7ab1c7c. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The NW_GCC video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: 06498d5 ("dt-bindings: clock: qcom: Add Nord Global Clock Controller") Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-1-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The global clock controller video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-2-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add compatible string for Nord video clock controller and the bindings for Nord Qualcomm SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-3-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
… Nord Update the compatible and the bindings for CAMCC support on Nord SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-4-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Nord shares the video clock controller topology with Glymur, differing only in the PLL0 hardware (Lucid-OLE vs Taycan-EKO-T) and the MVS0 frequency table. Extend the existing Glymur video clock controller driver to also probe on the qcom,nord-videocc compatible, switching to the Nord PLL configuration, VCO table, and MVS0 frequency table at probe time. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-5-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add support for the Camera Clock Controller (CAMCC) on the Nord platform for camera SW drivers to request for these clocks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-6-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…clocks Nord is reusing the Glymur videocc and thus include the correct header for the clocks to be referenced by consumers. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add a dedicated binding for the Qualcomm Nord SoC PAS devices: ADSP and CDSPs. Nord ADSP uses CX and MX power domains while the CDSPs add an NSP domain on top of that. Nord ADSP was previously documented in qcom,sm8550-pas.yaml, which hardcodes a two-entry power-domains list and therefore cannot express the third NSP domain the CDSPs require. Drop the Nord bits from that binding so Nord is described in exactly one place. This supersedes commit a602117 ("FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Document Nord ADSP"). Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Add support for the 4 CDSPs found on Nord SoC. Each CDSP uses the CX, MX and NSP power domains, and is cold booted by Linux, so no early_boot flag is needed unlike the Nord ADSP. The device tree nodes for these already exist in nord.dtsi, with the power domains and XO clock supplied from nord-embedded.dtsi, but the driver had no matching resource descriptors, so the CDSP nodes did not probe. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances and the PCIe SMMU (SMMUv3) nodes. Wire up the gpucc clock and power domain on both adreno SMMU nodes in nord-embedded.dtsi for embedded Nord variants where gpucc is available. Change-Id: I5ca3ccace0b109aedad82879af5d5956155df422 Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
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Summary
CONFIG_QCOM_IOMMU_DEBUG) with debugfs-based profiling and ATOS testing supportiommu_test_devicenode tonord-rrdandnord-ride-sxusingapps_smmu_0SID0x0001reserved for IOMMU debug useTest plan
CONFIG_QCOM_IOMMU_DEBUG=yand verify no errors/sys/kernel/debug/iommu/on nord-rrd and nord-ride-sx targets🤖 Generated with Claude Code