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macio: Keep interrupt events and CPU IRQ state consistent - #242

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dingusdev merged 1 commit into
dingusdev:masterfrom
mihaip:upstream-heathrow-irq
Oct 15, 2026
Merged

dingusdev merged 1 commit into
dingusdev:masterfrom
mihaip:upstream-heathrow-irq

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@mihaip

@mihaip mihaip commented Oct 15, 2026

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Apply the Grand Central fixes from #240 to O'Hare/Heathrow/Paddington; the Heathrow ERS shows that it expects to have the same behavior:

  • Reevaluate the CPU interrupt when either mask changes, releasing it if no pending events remain enabled in either bank (section 7.1).
  • Keep events latched until software writes InterruptClear, even if a device deasserts its interrupt line or repeats an assertion (sections 7.2.1 and 7.2.5).
  • Replace writable InterruptMask2 bits instead of ORing them, allowing sources to be disabled while preserving the read-only IntMode bit (section 7.2.6).

Apply the Grand Central fixes from dingusdev#240 to O'Hare,
Heathrow, and Paddington; the Heathrow ERS shows that it expects to
have the same behavior:
- Reevaluate the CPU interrupt when either mask changes, releasing it
  if no pending events remain enabled in either bank (section 7.1).
- Keep events latched until software writes InterruptClear, even if a
  device deasserts its interrupt line or repeats an assertion (sections
  7.2.1 and 7.2.5).
- Replace writable InterruptMask2 bits instead of ORing them, allowing
  sources to be disabled while preserving the read-only IntMode bit
  (section 7.2.6).
@dingusdev
dingusdev merged commit 357b838 into dingusdev:master Oct 15, 2026
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@mihaip
mihaip deleted the upstream-heathrow-irq branch October 16, 2026 21:32
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2 participants