[PW_SID:1145985] clk: microchip: mpfs: fix regmap_update_bits() mask/val order - #2472
[PW_SID:1145985] clk: microchip: mpfs: fix regmap_update_bits() mask/val order#2472linux-riscv-bot wants to merge 2 commits into
Conversation
mpfs_cfg_clk_set_rate() passes the mask and value arguments to regmap_update_bits() in the wrong order. The resulting write becomes reg = orig_reg | val, causing bits to not be cleared if the clock divider changes. Pass the arguments in the correct order so the divider field is updated as intended. Fixes: c6f2ddd ("clk: microchip: mpfs: use regmap for clocks") Signed-off-by: Pedro Kopper <pedro.kopper@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
|
Patch 1: "clk: microchip: mpfs: fix regmap_update_bits() mask/val order" |
bb1a926 to
6f6f7c0
Compare
PR for series 1145985 applied to workflow__riscv__fixes
Name: clk: microchip: mpfs: fix regmap_update_bits() mask/val order
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1145985
Version: 1