[PW_SID:1147013] RISC-V: errata: Add SiFive MAL-9092 workaround - #2482
[PW_SID:1147013] RISC-V: errata: Add SiFive MAL-9092 workaround#2482linux-riscv-bot wants to merge 4 commits into
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…_RWX When CONFIG_STRICT_MODULE_RWX is not set, execmem cannot create temporary writable mappings for read-only executable pages. In this case, the execmem ranges must already have writable permissions. Currently EXECMEM_KPROBES unconditionally uses PAGE_KERNEL_READ_EXEC, which causes kprobe instruction slot writes to trigger page faults on systems where CONFIG_STRICT_MODULE_RWX is not enabled. Fix this by using PAGE_KERNEL_EXEC when CONFIG_STRICT_MODULE_RWX is not available. Signed-off-by: Xiaofeng Yuan <xiaofengmian@163.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Nam Cao <namcao@linutronix.de> Link: https://patch.msgid.link/20260814082742.148403-2-xiaofengmian@163.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
patch_map() always creates a temporary writable mapping via fixmap for kernel text addresses, even when CONFIG_STRICT_KERNEL_RWX is disabled and the kernel text is already mapped with _PAGE_WRITE. This is unnecessary overhead at best, and on minimal configurations it can cause page faults. Skip the fixmap path for kernel text when CONFIG_STRICT_KERNEL_RWX is not enabled, since the text pages are already writable in that case. The module text path is already gated on CONFIG_STRICT_MODULE_RWX and is kept unchanged. Reported-by: Klara Modin <klara@kasm.eu> Closes: https://lore.kernel.org/all/ant_8TaBbov_GS4i@soda.int.kasm.eu/ Reported-by: Lad Prabhakar <prabhakar.csengg@gmail.com> Closes: https://lore.kernel.org/all/CA+V-a8tQK8rih9SGGTyqrEBGpNkx4H0eX2YccCRrgkVAPr+EBg@mail.gmail.com/ Tested-by: Klara Modin <klarasmodin@gmail.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20260814082742.148403-3-xiaofengmian@163.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
SiFive cores with MAL-9092 require fence.rw instructions around HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering when accessing guest memory. Note that HSTATUS.HU is cleared during KVM initialization, restricting hypervisor instructions to HS-mode only. If future changes enable HSTATUS.HU for U-mode access, additional errata considerations will be needed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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Patch 1: "RISC-V: errata: Add SiFive MAL-9092 workaround" |
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PR for series 1147013 applied to workflow__riscv__fixes
Name: RISC-V: errata: Add SiFive MAL-9092 workaround
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1147013
Version: 1