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[PW_SID:1148328] bpf, riscv: Add support for signed arena loads #2494

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[PW_SID:1148328] bpf, riscv: Add support for signed arena loads #2494

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2fe340b
bpf, riscv: Add support for signed arena loads
cp0613 Aug 19, 2026
18150eb
selftests/bpf: Enable arena LDSX tests for riscv64
cp0613 Aug 19, 2026
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16 changes: 10 additions & 6 deletions arch/riscv/net/bpf_jit_comp64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -777,6 +777,8 @@ static int add_exception_handler(const struct bpf_insn *insn, int dst_reg,
if (BPF_MODE(insn->code) != BPF_PROBE_MEM &&
BPF_MODE(insn->code) != BPF_PROBE_MEMSX &&
BPF_MODE(insn->code) != BPF_PROBE_MEM32 &&
!(BPF_MODE(insn->code) == BPF_PROBE_MEM32SX &&
BPF_CLASS(insn->code) == BPF_LDX) &&
BPF_MODE(insn->code) != BPF_PROBE_ATOMIC)
return 0;

Expand Down Expand Up @@ -1902,13 +1904,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
case BPF_LDX | BPF_PROBE_MEM32 | BPF_H:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
/* LDX | PROBE_MEM32SX: sign-extending arena load */
case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B:
case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H:
case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W:
{
bool sign_ext;

sign_ext = BPF_MODE(insn->code) == BPF_MEMSX ||
BPF_MODE(insn->code) == BPF_PROBE_MEMSX;
BPF_MODE(insn->code) == BPF_PROBE_MEMSX ||
BPF_MODE(insn->code) == BPF_PROBE_MEM32SX;

if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) {
if (BPF_MODE(insn->code) == BPF_PROBE_MEM32 ||
BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) {
emit_add(RV_REG_T2, rs, RV_REG_ARENA, ctx);
rs = RV_REG_T2;
}
Expand Down Expand Up @@ -2126,10 +2134,6 @@ bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena)
if (insn->imm == BPF_CMPXCHG)
return rv_ext_enabled(ZACAS);
break;
case BPF_LDX | BPF_MEMSX | BPF_B:
case BPF_LDX | BPF_MEMSX | BPF_H:
case BPF_LDX | BPF_MEMSX | BPF_W:
return false;
}
}

Expand Down
17 changes: 17 additions & 0 deletions tools/testing/selftests/bpf/progs/verifier_ldsx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -286,6 +286,19 @@ __jited("add x11, x0, x28")
__jited("ldrsh x22, [x11, #0x18]")
__jited("add x11, x0, x28")
__jited("ldrsb x22, [x11, #0x20]")
__arch_riscv64
__jited("add t2, a5, s7")
__jited("lw s3, 0x10(t2)")
__jited("add t2, a5, s7")
__jited("lh s3, 0x18(t2)")
__jited("add t2, a5, s7")
__jited("lb s3, 0x20(t2)")
__jited("add t2, a0, s7")
__jited("lw s4, 0x10(t2)")
__jited("add t2, a0, s7")
__jited("lh s4, 0x18(t2)")
__jited("add t2, a0, s7")
__jited("lb s4, 0x20(t2)")
__naked void arena_ldsx_disasm(void *ctx)
{
asm volatile (
Expand Down Expand Up @@ -317,6 +330,7 @@ __description("Arena LDSX Exception")
__success __retval(0)
__arch_x86_64
__arch_arm64
__arch_riscv64
__naked void arena_ldsx_exception(void *ctx)
{
asm volatile (
Expand All @@ -338,6 +352,7 @@ __description("Arena LDSX, S8")
__success __retval(-1)
__arch_x86_64
__arch_arm64
__arch_riscv64
__naked void arena_ldsx_s8(void *ctx)
{
asm volatile (
Expand Down Expand Up @@ -369,6 +384,7 @@ __description("Arena LDSX, S16")
__success __retval(-1)
__arch_x86_64
__arch_arm64
__arch_riscv64
__naked void arena_ldsx_s16(void *ctx)
{
asm volatile (
Expand Down Expand Up @@ -400,6 +416,7 @@ __description("Arena LDSX, S32")
__success __retval(-1)
__arch_x86_64
__arch_arm64
__arch_riscv64
__naked void arena_ldsx_s32(void *ctx)
{
asm volatile (
Expand Down