[PW_SID:1149425] [v2] riscv: Add native this_cpu_cmpxchg() support - #2510
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[PW_SID:1149425] [v2] riscv: Add native this_cpu_cmpxchg() support#2510linux-riscv-bot wants to merge 1 commit into
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RISC-V falls back to the generic this_cpu_cmpxchg() implementation, which serializes the operation by disabling local interrupts. Consequently, HAVE_CMPXCHG_LOCAL is unset and users such as percpu_counter cannot use their cmpxchg-based fast paths. Implement the 4-byte this_cpu_cmpxchg() operation with cmpxchg_local(), and provide the 8-byte operation on RV64. Pin execution while resolving the current CPU pointer so the LR/SC loop operates on one per-CPU instance, while allowing interrupt-context updates to race through the atomic operation. Provide this_cpu_cmpxchg128() on RV64 when the kernel and toolchain support the Zacas extension, using cmpxchg128_local(). Changes in v2: - Add the RV64 Zacas-gated this_cpu_cmpxchg128() implementation. - Rebase and test against latest upstream. Copy the old and new values to private temporaries before invoking cmpxchg_local(). This avoids collisions between local variable names in nested statement-expression macros. The 1- and 2-byte operations continue to use the generic fallback. Select HAVE_CMPXCHG_LOCAL and update the architecture feature matrix. Tested on latest upstream commit 7f063b2 with GCC 15.2: RV32 and RV64 builds of arch/riscv/kernel/ and lib/percpu_counter.o pass, and an RV64 compile probe emits amocas.q for this_cpu_cmpxchg128(). Signed-off-by: Xie Bo <xb@ultrarisc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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PR for series 1149425 applied to workflow__riscv__fixes
Name: [v2] riscv: Add native this_cpu_cmpxchg() support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1149425
Version: 2