[PW_SID:1155588] riscv: dts: sophgo: sg2044: srd3: add spifmc node - #2567
[PW_SID:1155588] riscv: dts: sophgo: sg2044: srd3: add spifmc node#2567linux-riscv-bot wants to merge 5 commits into
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Overflow status and restart masks are u64, but bits were built with BIT(). On RV32 that is an unsigned long shift, so indices >= 32 truncate or wrap and corrupt the mask. Use BIT_ULL() for those u64 bitops. Fixes: a862521 ("drivers/perf: riscv: Implement SBI PMU snapshot function") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu <liuxixin@kylinos.cn> Link: https://patch.msgid.link/prpmask01bitul.v2.1786434000.git.liuxixin@kylinos.cn [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The available-counter mask was a single unsigned long, but iteration uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object. Filling with an unsigned-long bit at index 32 and above is also wrong. Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word into CFG_MATCH when checking events, when allocating an index, and when stopping all counters. Set the counter base to i times BITS_PER_LONG. Share the CFG_MATCH ecall through a small helper so the 32-bit argument split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits above XLEN set, so the first word alone is not enough. Fixes: e999143 ("RISC-V: Add perf platform driver based on SBI PMU extension") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu <liuxixin@kylinos.cn> Link: https://patch.msgid.link/prpmask02cmap.v2.1786434000.git.liuxixin@kylinos.cn [pjw@kernel.org: updated to apply; fixed checkpatch.pl issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The RISC-V ISA manual specifies that Zfh implies Zfhmin, a normative rule clarified in riscv/riscv-isa-manual#3070. Zvfh likewise implies Zvfhmin, as stated by the vector extension specification. The kernel currently reports ZFH and ZFHMIN (and ZVFH and ZVFHMIN) as independent hwprobe bits derived only from what the device tree declares. Platforms that declare just "zfh" (Zfh being a superset that already contains all Zfhmin instructions) therefore report RISCV_HWPROBE_EXT_ZFHMIN=0, which breaks userspace RVA23 conformance checks (e.g. snapd installing core26 on riscv64). Use the existing superset mechanism to set the implied subset bits: - zfh implies zfhmin - zvfh implies zvfhmin Add a hwprobe selftest asserting the implication holds and update the hwprobe documentation accordingly. This is complementary to the rva23u64 base behavior discussion: the RVA23 conformance query proposed there is derived from the per-extension bits fixed here, so correct EXT_0 reporting is a prerequisite for it to work on harts whose device tree declares only "zfh". Tested on a RISC-V QEMU VM whose device tree only declares "zfh" and "zvfh": with this change both /proc/cpuinfo and the hwprobe RISCV_HWPROBE_KEY_IMA_EXT_0 bitmap report ZFHMIN and ZVFHMIN, and the hwprobe selftest (including the new implication check) passes. Link: https://lore.kernel.org/kvm-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/ Signed-off-by: JinRui <jinrui@haiwei.tech> Link: https://patch.msgid.link/7190E4DB338251C3+20260811081513.2849980-1-jinrui@haiwei.tech [pjw@kernel.org: trimmed superfluous blank line in tags] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The SRD3-10 board has two spiflash. Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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Patch 1: "riscv: dts: sophgo: sg2044: srd3: add spifmc node" |
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PR for series 1155588 applied to workflow__riscv__fixes
Name: riscv: dts: sophgo: sg2044: srd3: add spifmc node
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1155588
Version: 1