[PW_SID:1155693] riscv: Add Ssqosid and initial CBQRI resctrl support - #2569
[PW_SID:1155693] riscv: Add Ssqosid and initial CBQRI resctrl support#2569linux-riscv-bot wants to merge 10 commits into
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Overflow status and restart masks are u64, but bits were built with BIT(). On RV32 that is an unsigned long shift, so indices >= 32 truncate or wrap and corrupt the mask. Use BIT_ULL() for those u64 bitops. Fixes: a862521 ("drivers/perf: riscv: Implement SBI PMU snapshot function") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu <liuxixin@kylinos.cn> Link: https://patch.msgid.link/prpmask01bitul.v2.1786434000.git.liuxixin@kylinos.cn [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The available-counter mask was a single unsigned long, but iteration uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object. Filling with an unsigned-long bit at index 32 and above is also wrong. Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word into CFG_MATCH when checking events, when allocating an index, and when stopping all counters. Set the counter base to i times BITS_PER_LONG. Share the CFG_MATCH ecall through a small helper so the 32-bit argument split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits above XLEN set, so the first word alone is not enough. Fixes: e999143 ("RISC-V: Add perf platform driver based on SBI PMU extension") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu <liuxixin@kylinos.cn> Link: https://patch.msgid.link/prpmask02cmap.v2.1786434000.git.liuxixin@kylinos.cn [pjw@kernel.org: updated to apply; fixed checkpatch.pl issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The RISC-V ISA manual specifies that Zfh implies Zfhmin, a normative rule clarified in riscv/riscv-isa-manual#3070. Zvfh likewise implies Zvfhmin, as stated by the vector extension specification. The kernel currently reports ZFH and ZFHMIN (and ZVFH and ZVFHMIN) as independent hwprobe bits derived only from what the device tree declares. Platforms that declare just "zfh" (Zfh being a superset that already contains all Zfhmin instructions) therefore report RISCV_HWPROBE_EXT_ZFHMIN=0, which breaks userspace RVA23 conformance checks (e.g. snapd installing core26 on riscv64). Use the existing superset mechanism to set the implied subset bits: - zfh implies zfhmin - zvfh implies zvfhmin Add a hwprobe selftest asserting the implication holds and update the hwprobe documentation accordingly. This is complementary to the rva23u64 base behavior discussion: the RVA23 conformance query proposed there is derived from the per-extension bits fixed here, so correct EXT_0 reporting is a prerequisite for it to work on harts whose device tree declares only "zfh". Tested on a RISC-V QEMU VM whose device tree only declares "zfh" and "zvfh": with this change both /proc/cpuinfo and the hwprobe RISCV_HWPROBE_KEY_IMA_EXT_0 bitmap report ZFHMIN and ZVFHMIN, and the hwprobe selftest (including the new implication check) passes. Link: https://lore.kernel.org/kvm-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/ Signed-off-by: JinRui <jinrui@haiwei.tech> Link: https://patch.msgid.link/7190E4DB338251C3+20260811081513.2849980-1-jinrui@haiwei.tech [pjw@kernel.org: trimmed superfluous blank line in tags] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The overflow IRQ handler dereferences cpu_hw_evt before the null check. Move the check first. Defensive only; the cookie is valid on the normal path today. Fixes: a862521 ("drivers/perf: riscv: Implement SBI PMU snapshot function") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu <liuxixin@kylinos.cn> Link: https://patch.msgid.link/fdd42c791752.v2.1786420235.git.liuxixin@kylinos.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
Add support for the RISC-V CBQRI capacity controller. A platform driver passes a cbqri_controller_info descriptor together with the cache level to riscv_cbqri_register_cc_dt(), which probes the controller and adds it to the controller list. Assisted-by: Claude:claude-opus-4-8 Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Wire CBQRI capacity controllers into resctrl as RDT_RESOURCE_L2 and RDT_RESOURCE_L3 schemata. resctrl exposes a single cap set per rid, so when more than one capacity controller backs a cache level they must agree on those caps. A level whose controllers disagree is left unexposed. Other levels are unaffected. Control domains are created in the cpuhp online callback and keyed on the onlining CPU's cache id from cacheinfo, so a CPU that is offline at probe time still joins its domain once it comes online. A domain is published on the ctrl_domains RCU list only after it is fully initialized and brought online, and removed from the list before it is taken offline, following the documented safe traversal rules. Assisted-by: Claude:claude-opus-4-8 Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Make RISCV_CBQRI a user-selectable option (default y) that depends on RISCV_ISA_SSQOSID, rather than having RISCV_ISA_SSQOSID select it unconditionally. A user with Ssqosid hardware can now build a kernel without the CBQRI resctrl support if they do not want it, while the default keeps it enabled. RISCV_CBQRI selects ARCH_HAS_CPU_RESCTRL, which makes RESCTRL_FS available on RISC-V, since resctrl is only meaningful when the CBQRI core that backs it is built. The resctrl filesystem integration is gated separately by RISCV_CBQRI_RESCTRL_FS, a silent option that defaults to y when both RISCV_CBQRI and RESCTRL_FS are enabled. Enabling the resctrl filesystem itself stays a user choice via the standard fs/Kconfig MISC_FILESYSTEMS menu. Signed-off-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Document the device tree binding for RISC-V CBQRI capacity and bandwidth controllers. Each controller is named by a device-specific compatible followed by the generic compatible. The binding also describes the common riscv,cbqri-rcid and riscv,cbqri-mcid properties, and the optional riscv,cbqri-cache phandle that links a capacity controller to the cache whose capacity it allocates. Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com> Signed-off-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a device-tree platform driver, bound to the generic riscv,cbqri-capacity-controller compatible, that registers a CBQRI capacity controller as the resctrl cache-allocation resource for the cache it governs. The driver follows the node's riscv,cbqri-cache phandle to that cache, reads its level, and matches it against cacheinfo to get the resctrl domain id. It then hands the controller to riscv_cbqri_register_cc_dt() with the riscv,cbqri-rcid count from the node. Nothing is vendor-specific, and the DT "reg" is the CBQRI register block itself, so any SoC that describes a CBQRI capacity controller in device tree can reuse the driver unchanged. Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 1: "[v7,1/5] riscv_cbqri: Add capacity controller probe and allocation device ops" |
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Patch 2: "[v7,2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask" |
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Patch 2: "[v7,2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask" |
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Patch 2: "[v7,2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask" |
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Patch 2: "[v7,2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask" |
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Patch 2: "[v7,2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask" |
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Patch 2: "[v7,2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask" |
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Patch 3: "[v7,3/5] riscv: Enable resctrl filesystem for Ssqosid" |
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Patch 3: "[v7,3/5] riscv: Enable resctrl filesystem for Ssqosid" |
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Patch 3: "[v7,3/5] riscv: Enable resctrl filesystem for Ssqosid" |
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Patch 3: "[v7,3/5] riscv: Enable resctrl filesystem for Ssqosid" |
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Patch 3: "[v7,3/5] riscv: Enable resctrl filesystem for Ssqosid" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 4: "[v7,4/5] dt-bindings: riscv: Add binding for CBQRI controllers" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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Patch 5: "[v7,5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver" |
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PR for series 1155693 applied to workflow__riscv__fixes
Name: riscv: Add Ssqosid and initial CBQRI resctrl support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1155693
Version: 7