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[PW_SID:990053] clk: spacemit: fix sspax_clk #751

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[PW_SID:990053] clk: spacemit: fix sspax_clk #751

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9e118ce
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
TroyMitchell911 Aug 11, 2025
4a0cddb
clk: spacemit: fix sspax_clk
TroyMitchell911 Aug 11, 2025
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29 changes: 25 additions & 4 deletions drivers/clk/spacemit/ccu-k1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -247,18 +247,37 @@ CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1),

CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);

static const struct clk_parent_data sspa_parents[] = {
/*
* When i2s_bclk is selected as the parent clock of sspa,
* the hardware requires bit3 to be set
*/
CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0);
CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0);

static const struct clk_parent_data sspa0_parents[] = {
CCU_PARENT_HW(pll1_d384_6p4),
CCU_PARENT_HW(pll1_d192_12p8),
CCU_PARENT_HW(pll1_d96_25p6),
CCU_PARENT_HW(pll1_d48_51p2),
CCU_PARENT_HW(pll1_d768_3p2),
CCU_PARENT_HW(pll1_d1536_1p6),
CCU_PARENT_HW(pll1_d3072_0p8),
CCU_PARENT_HW(i2s_bclk),
CCU_PARENT_HW(sspa0_i2s_bclk),
};
CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);

static const struct clk_parent_data sspa1_parents[] = {
CCU_PARENT_HW(pll1_d384_6p4),
CCU_PARENT_HW(pll1_d192_12p8),
CCU_PARENT_HW(pll1_d96_25p6),
CCU_PARENT_HW(pll1_d48_51p2),
CCU_PARENT_HW(pll1_d768_3p2),
CCU_PARENT_HW(pll1_d1536_1p6),
CCU_PARENT_HW(pll1_d3072_0p8),
CCU_PARENT_HW(sspa1_i2s_bclk),
};
CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);

CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0);
Expand Down Expand Up @@ -865,6 +884,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
[CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw,
[CLK_TSEN_BUS] = &tsen_bus_clk.common.hw,
[CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw,
[CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw,
[CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw,
};

static const struct spacemit_ccu_data k1_ccu_apbc_data = {
Expand Down
2 changes: 2 additions & 0 deletions include/dt-bindings/clock/spacemit,k1-syscon.h
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Original file line number Diff line number Diff line change
Expand Up @@ -182,6 +182,8 @@
#define CLK_SSPA1_BUS 97
#define CLK_TSEN_BUS 98
#define CLK_IPC_AP2AUD_BUS 99
#define CLK_SSPA0_I2S_BCLK 100
#define CLK_SSPA1_I2S_BCLK 101

/* APBC resets */
#define RESET_UART0 0
Expand Down
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