[PW_SID:992385] [V2] RISC-V: KVM: Write hgatp register with valid mode bits - #791
[PW_SID:992385] [V2] RISC-V: KVM: Write hgatp register with valid mode bits#791linux-riscv-bot wants to merge 1 commit into
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According to the RISC-V Privileged Architecture Spec, when MODE=Bare is selected,software must write zero to the remaining fields of hgatp. We have detected the valid mode supported by the HW before, So using a valid mode to detect how many vmid bits are supported. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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Patch 1: "[V2] RISC-V: KVM: Write hgatp register with valid mode bits" |
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PR for series 992385 applied to workflow__riscv__fixes
Name: [V2] RISC-V: KVM: Write hgatp register with valid mode bits
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=992385
Version: 2