[PW_SID:992893] [v3] riscv: fix using wrong load type - #800
[PW_SID:992893] [v3] riscv: fix using wrong load type#800linux-riscv-bot wants to merge 1 commit into
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thread_info.cpu field is 32 bits wide, but is accessed using an XLEN-bit load, which might be 64bit load, fix it Changes in v3: - replace space with tab to keep it aligned with code block - Add "Fixes" tag Changes in v2: - add a comment to explain why use lw instead of REG_L. - correct commit message Fixes: 503638e ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
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Patch 1: "[v3] riscv: fix using wrong load type" |
PR for series 992893 applied to workflow__riscv__fixes
Name: [v3] riscv: fix using wrong load type
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=992893
Version: 3