[PW_SID:994749] [01/18] riscv: add initial kconfig and build flags for big-endian - #824
[PW_SID:994749] [01/18] riscv: add initial kconfig and build flags for big-endian#824linux-riscv-bot wants to merge 18 commits into
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Add initial kconfig and makefile updates to get a base big-endian build for arch/riscv. Will require header updates for IO code and features whcih are known to not work. Make this depend on CONFIG_EXPERIMENTAL for now as there are bits that have not been fully fixed to work big-endian. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add checks for big-endian, using BYTE_ORDER as modern compilers should define this and anything that isn't is probably too old to build a system. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
You can't build with vector enabled at the moment so remove this until gcc is changed. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Use the generic word at a time code if we're running in big endian for now otherwise this doesn't work. Add better support later. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Using .word breaks with big endian builds, making something which is not a valid or worse an instruction or pair that does something which is not intended. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This code does not currently build with big-endian so disable it for now. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The priveldged ISA spec says that all instructions should
be treated as little endian, so if we load them from memory
we should do le{16,32}_to_cpu on these and the reverse when
storing.
This fixes jump_label, bug and related functions for big endian
builds.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
If running big endian then the instruction stream needs to be written le16/le323 and the BPF BSWAP instrictions need to correctly set the endian. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Updated {k,u}probe code to deal with big endian mode where
the instruction stream is always in little endian.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Make the ftrace code work with big endian by ensuring the instruction stream is accessed little endian. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the trapped instruction (insn) as the second argument to riscv_v_first_use_handler() from the trap handler so when we add more handlers we can do the fetch of the instruction just once. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
If operating in big-endian, start all threads with UBE to keep them the same endian as the system. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Update the unaligned handling of memory when in big-endian and the byte positions inside a loaded word change. Do this by wrapping the shift macros and swapping the left and right shfits. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
It would seem sensible to add an ASM_INSN() wrapper for anyone to use for hand assembly of instructions. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Start the guest in the same endian as the host. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The instructions are always little endian, so ensure the correct instruction endian. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
It seems a good idea if we get an undecoded instruction here to at-least print an error. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 1: "[01/18] riscv: add initial kconfig and build flags for big-endian" |
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Patch 16: "[16/18] KVM: riscv: add hstatus to allow endian control" |
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Patch 16: "[16/18] KVM: riscv: add hstatus to allow endian control" |
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Patch 16: "[16/18] KVM: riscv: add hstatus to allow endian control" |
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Patch 16: "[16/18] KVM: riscv: add hstatus to allow endian control" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 17: "[17/18] KVM: riscv: instructions are little endian" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
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Patch 18: "[18/18] KVM: riscv: add warning if undecoded instruction" |
2 participants
PR for series 994749 applied to workflow__riscv__fixes
Name: [01/18] riscv: add initial kconfig and build flags for big-endian
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=994749
Version: 1