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[PW_SID:994802] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 #825

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[PW_SID:994802] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 #825

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b1bdfd4
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
Aug 23, 2025
0f6f528
riscv: dts: starfive: jh7110: add DMC memory controller
Aug 23, 2025
06d0f21
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot l…
Aug 23, 2025
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74 changes: 74 additions & 0 deletions Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 DMC

maintainers:
- E Shattow <e@freeshell.de>

description:
JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
2133Mbps (up to 2800Mbps).

properties:
compatible:
items:
- const: starfive,jh7110-dmc

reg:
items:
- description: controller registers
- description: phy registers

clocks:
maxItems: 1

clock-names:
items:
- const: pll

resets:
items:
- description: axi
- description: osc
- description: apb

reset-names:
items:
- const: axi
- const: osc
- const: apb

required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names

additionalProperties: false

examples:
- |
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
soc {
#address-cells = <2>;
#size-cells = <2>;

memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
};
};
24 changes: 24 additions & 0 deletions arch/riscv/boot/dts/starfive/jh7110.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@

cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
Expand Down Expand Up @@ -68,6 +69,7 @@

cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
Expand Down Expand Up @@ -101,6 +103,7 @@

cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
Expand Down Expand Up @@ -134,6 +137,7 @@

cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
Expand Down Expand Up @@ -167,6 +171,7 @@

cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
Expand Down Expand Up @@ -273,12 +278,14 @@

gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
compatible = "fixed-clock";
bootph-pre-ram;
clock-output-names = "gmac1_rgmii_rxin";
#clock-cells = <0>;
};

gmac1_rmii_refin: gmac1-rmii-refin-clock {
compatible = "fixed-clock";
bootph-pre-ram;
clock-output-names = "gmac1_rmii_refin";
#clock-cells = <0>;
};
Expand Down Expand Up @@ -321,6 +328,7 @@

osc: oscillator {
compatible = "fixed-clock";
bootph-pre-ram;
clock-output-names = "osc";
#clock-cells = <0>;
};
Expand Down Expand Up @@ -354,6 +362,7 @@
clint: timer@2000000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
bootph-pre-ram;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
Expand Down Expand Up @@ -880,6 +889,7 @@
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
bootph-pre-ram;
clocks = <&osc>, <&gmac1_rmii_refin>,
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
Expand All @@ -904,6 +914,7 @@

pllclk: clock-controller {
compatible = "starfive,jh7110-pll";
bootph-pre-ram;
clocks = <&osc>;
#clock-cells = <1>;
};
Expand Down Expand Up @@ -931,6 +942,19 @@
<&syscrg JH7110_SYSRST_WDT_CORE>;
};

memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
bootph-pre-ram;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
};

crypto: crypto@16000000 {
compatible = "starfive,jh7110-crypto";
reg = <0x0 0x16000000 0x0 0x4000>;
Expand Down
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