stm32/sdcard: Keep SDIO HW flow control disabled on STM32F4. - #148
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iabdalkader merged 1 commit intoAug 14, 2026
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Hardware flow control was enabled for the SD bus in the 2021 SDIO DMA
rework to avoid FIFO under/overruns, but on STM32F4 the SDIO hardware
flow control is broken: per the STM32F4 errata sheets, enabling it
causes glitches on SDIOCLK that corrupt data written to the card. The
failure only occurs when flow control actually engages, so it depends on
the card: on an OpenMV Cam M4 with a UHS-I class 64GB SDXC card every
write failed with a data CRC error (single block) or data timeout (multi
block) while reads worked perfectly.
Keep hardware flow control disabled on STM32F4 only, matching the errata
workaround ("do not use HW flow control"), and leave it enabled on
F7/H7/N6 where it works. Verified on the failing board: with this
change single and multi-block writes complete and verify correctly
(7.9MB/s file writes on the same card), and SD regression runs on
STM32F765 and STM32H743 boards are unaffected.
Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
iabdalkader
approved these changes
Aug 14, 2026
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Summary
SD card writes on STM32F4 boards can fail 100% of the time with certain cards —
every write returns a data CRC error (single block) or data timeout (multi
block) while reads work perfectly. On an OpenMV Cam M4 with a UHS-I class 64GB
SDXC card, all SD writes have been failing this way.
Root cause: hardware flow control was enabled for the SD bus in the 2021 SDIO
DMA rework
(openmv/micropython@
9cd5a200a,"Use temporary DMA buffer for SDIO transfers", to avoid FIFO under/overruns),
but the STM32F4's SDIO hardware flow control is broken silicon — per the
STM32F4 errata sheets, enabling it causes glitches on SDIOCLK that corrupt data
written to the card, and the documented workaround is "do not use HW flow
control". The failure only manifests when flow control actually engages, which
depends on the card/timing combination — which is why it has gone unnoticed
since early 2021 with many cards.
This keeps hardware flow control disabled on STM32F4 only. F7/H7/N6 keep it
enabled, where it works correctly and preserves the original under/overrun
mitigation.
Testing
clearing
CLKCR.HWFC_ENat runtime immediately made single- and multi-blockwrites complete with read-back verification passing, on the same card that
failed 100% before. Card checked for CSD write-protect bits (clear) to rule
out card-side protection.
7.9 MB/s (reads 9.7 MB/s) with content verification passing, previously 0%
write success.
OpenMV Cam H7 (STM32H743) are unaffected — those keep flow control enabled
and their speeds are unchanged (M7: 6.2/10.3 MB/s W/R, H7: 12.2/21.7 MB/s
W/R).
Trade-offs and Alternatives
Without hardware flow control, the F4 relies on DMA keeping the FIFO fed (which
the 2021 rework already forces) — the same configuration upstream MicroPython
has always shipped for F4, so under/overrun exposure is no worse than upstream.
The alternative of reverting flow control on all MCUs was rejected: it works on
F7/H7/N6 and serves its purpose there; only the F4 has the erratum.