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arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes #930

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Merged
Shiraz Hashim (shashim-quic) merged 1 commit into from
Aug 11, 2026
+97 −1
Merged

arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes #930

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12 changes: 12 additions & 0 deletions arch/arm64/boot/dts/qcom/nord-embedded.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2228,3 +2228,15 @@
maximum-speed = "high-speed";
qcom,select-utmi-as-pipe-clk;
};

&adreno_smmu_0 {
clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
clock-names = "hlos";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
};

&adreno_smmu_1 {
clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
clock-names = "hlos";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
};
86 changes: 85 additions & 1 deletion arch/arm64/boot/dts/qcom/nord.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2223,7 +2223,6 @@
reg = <0x0 0x15e00000 0x0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
interrupts = <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 225 IRQ_TYPE_LEVEL_HIGH>,
Expand Down Expand Up @@ -2321,6 +2320,91 @@
<GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};

adreno_smmu_0: iommu@3da0000 {
compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;

power-domains = <&scmi15_pd 0>;
power-domain-names = "power";
};

adreno_smmu_1: iommu@98a0000 {
compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x098a0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 932 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 937 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 938 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 939 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 940 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 941 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 924 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};

pcie_smmu: iommu@9980000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x9980000 0x0 0x20000>;
interrupts = <GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
#iommu-cells = <1>;
};

intc: interrupt-controller@17000000 {
Expand Down
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