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Revert "arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes" #938

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Merged
Shiraz Hashim (shashim-quic) merged 1 commit into from
Aug 12, 2026
Merged

Revert "arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes" #938

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100 changes: 1 addition & 99 deletions arch/arm64/boot/dts/qcom/nord.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2329,7 +2329,6 @@
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
Expand All @@ -2356,9 +2355,7 @@
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;

power-domains = <&scmi15_pd 0>;
power-domain-names = "power";
dma-coherent;
};

adreno_smmu_1: iommu@98a0000 {
Expand Down Expand Up @@ -2407,101 +2404,6 @@
#iommu-cells = <1>;
};

adreno_smmu_0: iommu@3da0000 {
compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};

adreno_smmu_1: iommu@98a0000 {
compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x098a0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 963 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 961 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 965 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 966 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 967 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 968 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 969 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 970 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 971 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 972 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 973 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 974 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};

pcie_smmu: iommu@9980000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x09980000 0x0 0x20000>;
interrupts = <GIC_SPI 930 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 932 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 934 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq",
"cmdq-sync",
"gerror";
dma-coherent;
#iommu-cells = <1>;
};

intc: interrupt-controller@17000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17000000 0x0 0x10000>,
Expand Down
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