fix: power-latch false-trigger, RGB LED footprint regression, JST connector clarity

[thePunderWoman]

Summary

• Power latch false-trigger: battery-only testing showed the board powering on immediately with no button press. Root cause: PWR_BTN_SENSE's resistor divider idled at ~VSYS/2, which was enough to forward-bias D_OR1 directly, with or without a press. Fixes it with a small NPN inverter (R_INV_BASE1 / Q_INV1 / R_INV_PU1) between the button and the diode-OR, and removes the now-unneeded R_PWR_SENSE1. New parts matched to JLCPCB Basic-library equivalents (all confirmed via live JLC search). PCB layout, DRC-clean, and the power_control_layout diagrams/docs updated to match.
• RGB LED footprint regression: D_RGB1's Footprint had reverted to the old/stale large SK6812 PLCC4 part (the one that failed PCBWay's earlier assembly) in both the cached lib_symbols default and the instance override. Restored to the custom SK6812MINI-E-012 footprint in both places.
• JST battery connector orientation: PCBWay mounted BT1 vertically instead of horizontal. Verified via two independent distributor sources (JLC + LCSC) that the specified MPN (S2B-PH-K(LF)(SN)) is genuinely right-angle/horizontal — this was an assembly-side error, not a design bug. Made the Value/Description fields explicitly spell out RIGHT-ANGLE / HORIZONTAL so it's unambiguous in the exported BOM for next time.
• Minor: OLED connector symbol pin layout tidy (no net/functional change — pin-number-to-signal mapping unchanged), silkscreen tweaks.

Test plan

• kicad-cli sch erc on full schematic hierarchy — 0 errors, 1 pre-existing benign warning (lib_symbol_mismatch on D_RGB1 vs cached lib copy)
• kicad-cli pcb drc — 0 violations
• kicad-cli sch export netlist — verified new inverter nets (PWR_BTN_INV_BASE, PWR_BTN_TRIGGER) wired as intended
• scripts/jlc_match.py — all 3 new parts + BT1 still match correctly to Basic-library/expected LCSC part numbers
• Physical continuity check on next board rev (power-latch fix not yet validated on real hardware)

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