fix: latch gate-drive divider, floating buck EN, and missing accelerometer MPNs

[thePunderWoman]

Summary

Second round of power-latch fixes, found by cross-checking a friend's third-party static-analysis tool run against this project's own netlist and the real component datasheets (one of its four findings was a false positive — buck EN genuinely is wired, just with no defined rest state — the other three, plus one more found while re-deriving the math, were real):

• Latch gate-drive divider was too weak — R_LATCH_G1 raised from 10kΩ to 1MΩ. The old value formed an unintended divider with R_INV_PU1 across D_OR1, leaving only ~0.3V at Q_LATCH1's gate on a button press — nowhere near enough to turn it on. This means the inverter fix from the previous PR likely never actually latched on real hardware. Raised the pull-down instead of shrinking the pull-up so Q_INV1's idle state doesn't turn into a continuous mA-scale drain.
• Button-sense node was being loaded — R_INV_BASE1 originally tapped PWR_BTN_SENSE in series with R_BTN_PU1, sagging the MCU's own button-read node to ~1V at idle instead of near-VSYS. Repurposed into its own dedicated 100kΩ VSYS pull-up, decoupled via a new Schottky (D_INV_ISO1, BAT54W) so a press still pulls the base low without loading the shared sense node.
• Buck's EN pin had no defined rest state — added R_PWR_EN_PD1 (100kΩ to GND). TI's TLV62569 datasheet explicitly says not to leave EN floating; previously its only connection was Q_PWR1's drain, with no pull either way.
• Missing MPNs filled in for U_ACCEL1, C_ACCEL_1/2/3 (leftover from the earlier accelerometer PR).
• Retired the JLCPCB Basic-library matching preference — no longer targeting JLCPCB assembly for this board, so that cost optimization no longer applies (still filling in real MF/MPN for every part regardless).
• power_control_layout diagrams (svg/md/html) updated to match all of the above.

Test plan

• kicad-cli sch erc on the full schematic hierarchy — 0 errors, 1 pre-existing benign warning (unrelated lib_symbol_mismatch on D_RGB1)
• kicad-cli sch export netlist — verified every new/changed net by hand (PWR_LATCH_G, PWR_BTN_INV_BASE, PWR_EN, etc.)
• kicad-cli pcb drc — 0 violations, 0 unconnected pads
• Full BOM re-run — every part now has MF/MPN populated, no gaps
• Production files regenerated (gerbers, BOM, CPL, JLC zip)
• Physical continuity/bring-up check on next board rev (still not yet validated on real hardware)

🤖 Generated with Claude Code