fix: add C_LATCH_G1 to stop a ~2ms PWR_EN blip on battery insertion

[thePunderWoman]

Summary

Follow-up to #59. A validator run claimed the board would power itself on whenever a battery is connected and could not stay off. With no physical board yet to bench-test, I simulated the button/inverter/latch circuit in ngspice (KiCad's bundled libngspice, driven from Python) instead.

The validator's claim doesn't hold:

• Off state: the Q_INV1 base sits at ~0.6–0.72V, so the inverter stays on. The button node is only grounded through R_BTN_PU1 (100kΩ), so D_INV_ISO1 can't clamp the base down to 0.3V.
• Shutdown: a fast 3V3 collapse never lifts PWR_LATCH_G (stays at 0V) — no re-trigger.
• Press: latches within ~0.1ms at VSYS 3.0 / 3.7 / 4.2V, including worst-case FET thresholds at 3.0V.

But it did surface a real, minor transient (pre-existing: ~1.4ms with the old VSYS pull-up, ~1.9ms now): on battery insertion Q_INV1 isn't conducting until C_DBNC1 charges through D_INV_ISO1, so PWR_LATCH_G briefly rises to ~VSYS−0.6V and PWR_EN pulses high ~1.9ms. It does not latch on; whether a 2ms buck-enable pulse is harmless depends on ESP32 boot timing, which I did not simulate.

Fix: C_LATCH_G1 — 100nF 0402 (same Samsung part as C_DBNC1, so no new BOM line) from PWR_LATCH_G to GND. Simulated peak gate voltage drops to ~0.33V, under the AO3400A's minimum threshold. 100nF chosen over 47nF, which peaked at ~0.65V, right at a minimum-threshold part. Cost: 4–8ms of added press latency; release also holds slightly longer.

• Also adds scripts/spice/latch_sim.py (+ README): the simulation used here, as a rerunnable check with pass/fail assertions (--cap 0 reproduces the insertion blip; exit code 1 on failure). Plus KiCad's reordered used-designators in snips_controller.kicad_pro.
• Layout diagrams/docs updated (callout I, routing step 8); production files regenerated.

Caveats

• Simulation uses generic SPICE models (2N3904-family for the MMBT3904, a fitted BAT54, Level-1 MOSFETs at typical/worst-case thresholds) — not vendor models. VSYS is an ideal source, the buck's EN load is ignored, and the ESP32 boot is not simulated.
• Still needs validation on the first real board.

Test plan

• kicad-cli sch erc — 0 errors, 1 pre-existing benign warning (D_RGB1 lib_symbol_mismatch)
• kicad-cli sch export netlist — C_LATCH_G1 pin 2 on PWR_LATCH_G, pin 1 on GND
• kicad-cli pcb drc — 0 violations, 0 unconnected pads; cap placed ~2.5–3mm from D_OR2 / R_LATCH_G1 / Q_LATCH1
• Every BOM part has MF/MPN
• Bench: on first real board, scope PWR_EN on battery insertion and confirm a held press latches at low battery

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