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A parameterized round robin arbiter, verified using pyuvm and UVM on EDA Playground

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Round Robin Arbiter with UVM Testbench

I worked through this on EDA Playground and the link is here; it seems as if you need an account to run code so I will host a pyuvm implementation on GitHub and include the UVM implementation here: https://edaplayground.com/x/NWPL

Adapted from Matt Weber's "Arbiters: Design Ideas and Coding Styles" and the FreeCores Verilog implementation

Weber: https://www.researchgate.net/publication/228693610_Arbiters_design_ideas_and_coding_styles

FreeCores: https://github.com/freecores/round_robin_arbiter

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A parameterized round robin arbiter, verified using pyuvm and UVM on EDA Playground

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