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OSVVM / AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component

Updated Sep 10, 2026
VHDL

mmxsrup / axi4-interface

Star

AXI4 and AXI4-Lite interface definitions

fpga systemverilog axi4 axi4-lite axi4-stream

Updated Sep 20, 2020
SystemVerilog

VHDL / Interfaces

Star

Interface definitions for VHDL-2019.

interface i2c vhdl uart ethernet record i2s mipi axi4 axi4-lite axi4-stream modeview

Updated May 13, 2026
VHDL

SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte-exact real-image round-trip tests. Verilator · Yosys · Docker · CI.

Updated Jul 5, 2026
SystemVerilog

rlee287 / hardware-bus-infrastructure

Star

A collection of formal properties for hardware buses, and cores using them.

psl sva wishbone-bus axi4 axi4-lite axi4-stream bus-standards

Updated Feb 22, 2021
Verilog

ReezanVisram / FPGA-RT-Audio-Visualizer

Star

A real-time audio visualizer on an FPGA. Receives and transmits audio packets via I2S, and displays the time-domain waveform of the input signal using VGA. Supports changing waveform and background colours via UART.

fpga hardware verilog uart vga i2s axi4-stream

Updated Sep 6, 2024
Verilog

chaffybird56 / isp-axi4

Star

Verilog image signal processor with AXI4-Stream interfaces — RTL ISP pipeline for FPGA SoC integration.

open-source computer-vision fpga embedded-systems rtl verilog hdl soc axi4 axi4-stream hardware-design image-signal-processing

Updated Jun 10, 2026
Python

mmxsrup / data2axi4s

Star

Convert data signal to axi4-stream signal

axi4-stream

Updated Mar 15, 2019
SystemVerilog

JN513 / verilog-buses-implementations

Sponsor

Star

Popular bus implementations in Verilog HDL

fpga i2c verilog spi i2c-bus avalon verilog-hdl apb ahb axi4 axi4-lite axi4-stream

Updated Feb 13, 2026
Verilog

amamory / hermes-2x2-noc-axis-ip

Star

A 2x2 mesh NoC compatible with AXI streaming interface

vivado network-on-chip axi-stream axi4-stream

Updated Aug 8, 2020
Coq

Dimakdrshv / UART_Controller

Star

Parametrizable UART controller in Verilog with AXI-Stream interface, configurable baud rate, oversampling ratio, parity mode, stop bits, and regression testbench for verification.

fpga rtl xilinx vivado uart testbench verilog-hdl axi4-stream

Updated Jun 16, 2026
Verilog

Ajayyyyyyyyyyy / axi-stream-bridge-uvm-verification

Star

Original UVM verification environment for a fictional AXI4-Stream-to-internal-bus bridge IP (StreamBridge) -- tag-indexed scoreboarding, split completer/DMA environments, wide-bus lane checking.

asic fpga verification systemverilog uvm axi4-stream