Cache-line false sharing linter for Rust structs
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May 25, 2026 - Rust
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mesi
Here are 10 public repositories matching this topic...
An in-depth project focusing on the design and simulation of a split L1 cache in C++. This repository covers MESI protocol operations, comprehensive test cases, and simulation results, showcasing strategies for enhancing cache coherence and performance. This is a class project from ECE 585: Microprocessor System Design at Portland State University
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Mar 23, 2024 - C++
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Nov 30, 2018 - C
Introduction to cache coherence: false sharing, MESI protocol and vectorization
processor-architecture workshop simd jmh simd-programming vectorization workshop-materials simd-instructions cache-invalidation jmh-benchmarks writeback mesi cache-line cache-coherence multi-core-architectures false-sharing cache-line-padding mesi-protocol writethrough cache-coherency
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Nov 16, 2024 - Java
Four-hart RV32IMA with MESI cache coherence, grown from my rv32-pipeline core; protocol model-checked, litmus-tested and shown failing in a museum of five classic bugs
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Oct 6, 2026 - C
C++20 split L1 cache model (8-way data, 4-way instruction) with simplified MESI and pseudo-LRU; fixed an I-cache way-0 lookup bug, locked in with a 14-trace golden regression.
cpp cpu-cache computer-architecture cache-simulator memory-hierarchy mesi cache-coherence write-back pseudo-lru
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Sep 24, 2026 - C++
A C++ concurrency learning repository with implementations of various synchronization primitives and concurrent data structures.
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Nov 1, 2025 - C++
Simulador de coherencia Cache de un procesador Multinucleo: protocolo MESI - 1 cache por Nucleo - Universidad Nacional Patagónica San Juan Bosco - OPEN SOURCE
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Sep 9, 2026 - JavaScript
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