B.Sc. graduate in Electrical and Computer Engineering from Ben-Gurion University of the Negev, specializing in VLSI and Control Systems.

I work on FPGA design, embedded systems and analog IC design. The full reports are in engineering-portfolio.

• Final project: Reliable High-Speed Networking on FPGA. TCP, UDP and a hardware UDP++ reliability layer on Zynq-7000 and VCU118. UDP++ reaches 692 Mbps at 512 B with a median RTT of 507 µs.
• 4 GHz current starved ring VCO in 180 nm CMOS. 134 µW at 4 GHz and -72.9 dBc/Hz phase noise at 1 MHz offset.
• MicroBlaze SoC design flow. Five-chapter report from RTL to a custom AXI4-Lite IP and DDR integration.

VHDL, C, Tcl, Vivado, Vitis, ModelSim, Cadence Virtuoso, KiCad, Wireshark, Git

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