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Keep unconnected instance ports when generating Verilog - #68

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aamir-azeez:fix/unconnected-instance-ports
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aamir-azeez wants to merge 1 commit into
PyHDI:developfrom
aamir-azeez:fix/unconnected-instance-ports

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@aamir-azeez

@aamir-azeez aamir-azeez commented Sep 27, 2026 •

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Fixes #58 reported by @darcy-wu.

Keep unconnected ports as empty arguments when writing an instance. In the past, .A() was passed as None to the expression visitor and caused a TypeError. The existing visitor is still used for connected ports.

The existing instance tests pass. Icarus preprocessing and the full test suite were not run.

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read_verilog_module does not support instances with unconnected ports, will generate a TypeError.

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