Pinned Loading

1. Cloneless1 Cloneless1 Public

   Cloneless1 is an open-source tamper-resistant cryptographic ASIC design

   VHDL 27 3

2. Cloneless2 Cloneless2 Public

   Cloneless2 is an open-source tamper-resistant cryptographic ASIC design

   VHDL 1 1

3. FOSSi_Tutorial FOSSi_Tutorial Public

   Hands-on material for a tutorial on the open silicon back-end.

   VHDL 2

4. uclcrypto/randomness_for_hardware_masking uclcrypto/randomness_for_hardware_masking Public

   Randomness Generation for Secure Hardware Masking - Unrolled Trivium to the Rescue

   VHDL 4

5. uclcrypto/prime_field_masking_hardware uclcrypto/prime_field_masking_hardware Public

   VHDL 1

6. uclcrypto/prime_masking_verification uclcrypto/prime_masking_verification Public

   (Formal) Verification of Circuits Masked over Prime-Order Fields

   Verilog 1