This is a tutorial on the open silicon back-end based on GlobalFoundries' open-source GF180MCU PDK, the wafer.space project template, and the LibreLane open-source EDA tool. We implement the Trivium stream cipher which is a popular choice for efficient concurrent pseudo-randomness generation in hardware masking schemes. All commands have been tested on Ubuntu 26.04.01 LTS. Using a (virtual) machine with at least 8 GB of memory and 2 cores is recommended.
To get started we first need to install LibreLane. It is provided as a nix-based reproducible build cached by the FOSSi foundation and can be installed using the following commands on Ubuntu:
sudo apt update
sudo apt install -y curl
curl --proto '=https' --tlsv1.2 -fsSL https://artifacts.nixos.org/nix-installer | sh -s -- install --no-confirm --extra-conf "
extra-substituters = https://nix-cache.fossi-foundation.org
extra-trusted-public-keys = nix-cache.fossi-foundation.org:3+K59iFwXqKsL7BNu6Guy0v+uTlwsxYQxjspXzqLYQs=
extra-experimental-features = nix-command flakes
"
. /nix/var/nix/profiles/default/etc/profile.d/nix-daemon.sh
nix-channel --add https://nixos.org/channels/nixpkgs-unstable
nix-channel --update
To clone this repository and start a nix shell you may execute the following commands:
sudo apt install -y git
git clone https://github.com/ThorbenMoos/FOSSi_Tutorial
cd FOSSi_Tutorial
nix-shell
Within the nix-shell the librelane command is available in addition to a number of other useful utilities. Try running librelane --help and have a quick look at its usage (no need to read it all).
To clone the GF180MCU PDK, in particular its standard IO library and 7 track standard cell library, run the following command:
ciel enable f6eeac7dad085ffcc829ccfd721f7b4ce39edcf7 --pdk-root gf180mcu --pdk-family gf180mcuD --include-libraries gf180mcu_fd_io --include-libraries gf180mcu_fd_sc_mcu7t5v0
You may have a look at the 3D geometries of the cells contained in these two libraries at https://agentdavo.github.io/GDS3D.
Navigate to the Trivium_Chip_Macro/macros/Trivium directory:
cd Trivium_Chip_Macro/macros/Trivium
Take a look at the Trivium.vhd source file and try to understand how the module works. Note the "output_bits" generic (equivalent to a Verilog parameter) which determines how many keystream bits the module produces per clock cycle. A corresponding testbench for output_bits=4 is provided in the Testbenches subfolder. Then open the Trivium.yaml configuration file and have a look at the different parameters. In particular, try to understand the "CLOCK_PERIOD" and "FP_CORE_UTIL" parameters, if needed with the help of the LibreLane documentation. Since LibreLane does not support VHDL, we first need to quickly convert the RTL code into Verilog:
ghdl -a Trivium.vhd
ghdl synth --out=verilog Trivium > Trivium.v
Now we can perform the full automated librelane flow to produce a clean GDS-II file implementing the Trivium module:
librelane Trivium.yaml --pdk gf180mcuD --pdk-root ../../../gf180mcu --manual-pdk
On a machine with 8GB RAM and 2 Cores, this should take about 8 minutes (can be significantly faster on bigger machines). While waiting you may want to pay some attention to the different flow steps that are executed and check the contents of the generated runs folder that are appearing as the tool progresses. If everything goes well, the tool should report all Antenna, LVS and DRC checks as "Passed". Congratulations, you have produced a manufacturable chip design! You can have a look at it using Klayout by prompting:
klayout runs/RUN*/final/gds/Trivium.gds
Take some time to inspect the GDS closely and play with the visibility of different layers. Now we can try to improve the macro's cost and performance by decreasing the "CLOCK_PERIOD" (e.g. to 10) and increasing the "FP_CORE_UTIL" (e.g. to 40) value in the Trivium.yaml configuration file. Then we can re-run the previous steps with the prepared Makefile by calling:
make all
While you are waiting, feel free to explore the runs folder to see the outputs of the different steps of the LibreLane flow. Once finished you can open the design in Klayout again and may notice that it has gotten smaller and more dense compared to before.
For this step we have integrated the Trivium design into a toplevel module that let's you provide the seed serially through a 4-bit bus. You may have a quick look at the FOSSi_Tutorial/Trivium_Chip_Macro/src/Trivium_Chip.vhd file. Then we have integrated the toplevel Trivium_Chip module into the wafer.space project template. You may have a look at FOSSi_Tutorial/Trivium_Chip_Macro/chip_top.sv and FOSSi_Tutorial/Trivium_Chip_Macro/chip_top.yaml to see how the IO pads, IO ring and hard macros are instantiated and placed. You may execute the entire flow with the prepared Makefile:
make all
On a machine with 8GB RAM and 2 Cores, this should take about 35 minutes (can be significantly faster on bigger machines), but you can see the intermediate results as they appear. The first GDS output should be ready a good 10 minutes before the finish. If everything goes well, the tool should report all Antenna and LVS checks as "Passed". Full DRC checks have not been performed for time reasons. They can be activated at the top of the chip_top.yaml file if you want to play around after the tutorial. Congratulations, you have produced a manufacturable chip design that can be submitted to a foundry for fabrication! You can open it in Klayout and have a look. If you have time, rerun this step with a different placement of the hard macro (specified in the chip_top.yaml file) to see how the optics of the GDS file change.
As an alternative to the previous flow of first pre-hardening a macro and then integrating it into a chip frame, you can also do everything in one go. For this, you may navigate to the FOSSi_Tutorial/Trivium_Chip folder and once again use the prepared Makefile:
make all
On a machine with 8GB RAM and 2 Cores, this should take about 35 minutes (can be significantly faster on bigger machines). If everything goes well, the tool reports all Antenna and LVS checks as "Passed". Full DRC checks have once again not been performed for time reasons. Open the chip design in Klayout and see how different it looks from the macro-based design. What do you notice?
If the previous tasks have been easy for you, you may now go ahead and increase the "output_bits" parameter in the FOSSi_Tutorial/Trivium_Chip/src/Trivium_Chip.vhd and adapt the FOSSi_Tutorial/Trivium_Chip/chip_top.sv and FOSSi_Tutorial/Trivium_Chip/chip_top.yamlfiles accordingly to instantiate sufficiently many IO cells for the larger output bus. There is plenty of space in the IO ring and on the chip. However, depending of your choice of output bits per cycle you may need to increase the clock period. Rerun the design and look at the result.