fix: keep button-sense within MCU rail, and add latch-gate margin at low battery

[thePunderWoman]

Summary

Two more findings from cross-checking a friend's static-analysis tool against our own netlist and datasheets, each verified before acting:

• PWR_BTN_SENSE over-voltage on GPIO2: R_BTN_PU1 pulled to VSYS, so the node idled up to ~4.5V on USB against the pin's ~3.6V (VDD+0.3V) ceiling — and back-fed the unpowered 3V3 rail through the pin's clamp diode (~30µA) whenever the MCU was off. Fix: R_BTN_PU1 now pulls up to 3V3. This is safe now because R_INV_BASE1 (last PR) gave the inverter its own VSYS pull-up. A resistor divider can't work here (VSYS spans 3.0–4.5V; the pin needs ≥2.5V to read high and ≤3.6V max), and a clamp would add a part and leave the back-feed. PCB reroute done (pad 1 → 3V3).
• Latch gate margin at low battery: with a realistic diode drop the gate reaches ~2.4V at VSYS=3.0V — no margin against the 2N7002's 2.5V worst-case threshold. Q_LATCH1 swapped to AO3400A (Vgs(th) max 1.45V, same SOT-23 G/S/D pinout, property-only change, no reroute).
• power_control_layout diagrams/docs updated (callouts D and H); production files regenerated.

Known trade-offs / bench watch-items

• With the pull-up on 3V3, the sense node takes ~14ms to charge after the rail comes up; firmware only reads it in the loop feeding a 3s hold detector, so this is harmless.
• Battery-insert glitch (hand analysis only, not new): Q_INV1 turns on only after C_DBNC1 charges to ~0.4V (~1ms). Worth scoping PWR_EN on battery insertion.

Test plan

• kicad-cli sch erc — 0 errors, 1 pre-existing benign warning (D_RGB1 lib_symbol_mismatch)
• kicad-cli sch export netlist — R_BTN_PU1 pin 1 on 3V3, pin 2 on PWR_BTN_SENSE
• kicad-cli pcb drc — 0 violations, 0 unconnected pads
• Every BOM part has MF/MPN
• Bench: confirm a held press latches power on at low battery, and scope PWR_EN on battery insert

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