Save casez statements in generated Verilog - #141
Open
aamir-azeez wants to merge 1 commit into
Open
aamir-azeez wants to merge 1 commit into
aamir-azeez wants to merge 1 commit into
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Fixes #137, reported by @Hinataee.
Use the existing case visitor and a separate template for
casez. Generic traversal previously omitted thecasezandendcasestatements and produced invalid Verilog. This completes code generation for the parser support added by Peter Birch in #57.The existing AST code-generator tests pass. Icarus preprocessing and the full test suite were not run.