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Save casez statements in generated Verilog - #141

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aamir-azeez wants to merge 1 commit into
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aamir-azeez:fix/casez-code-generation
Open

Save casez statements in generated Verilog#141
aamir-azeez wants to merge 1 commit into
PyHDI:developfrom
aamir-azeez:fix/casez-code-generation

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Commits on Sep 27, 2026