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PyHDI
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Save casez statements in generated Verilog
- #141
#141
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aamir-azeez
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PyHDI:develop
PyHDI/Pyverilog:develop
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aamir-azeez:fix/casez-code-generation
aamir-azeez/Pyverilog:fix/casez-code-generation
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Save casez statements in generated Verilog
#141
aamir-azeez
wants to merge 1 commit into
PyHDI:develop
PyHDI/Pyverilog:develop
from
aamir-azeez:fix/casez-code-generation
aamir-azeez/Pyverilog:fix/casez-code-generation
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Save casez statements in generated Verilog
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